Complementary MOSFET Research Articles

Hybrid Organic-Si C-MOSFET Image Sensor Designed with Blue-, Green-, and Red-Sensitive Organic Photodiodes on Si C-MOSFET-Based Photo Signal Sensor Circuit.

The resolution of Si complementary metal-oxide-semiconductor field-effect transistor (C-MOSFET) image sensors (CISs) has been intensively enhanced to follow the technological revolution of smartphones, AI devices, autonomous cars, robots, and drones, approaching the physical and material limits of a resolution increase in conventional Si CISs because of the low quantum efficiency (i.e., ~40%) and aperture ratio (i.e., ~60%). As a novel solution, a hybrid organic-Si image sensor was developed by implementing B, G, and R organic photodiodes on four n-MOSFETs for photocurrent sensing. Photosensitive organic donor and acceptor materials were designed with cost-effective small molecules, i.e., the B, G, and R donor and acceptor small molecules were Coumarin6 and C_60, DMQA and MePTC, and ZnPc and TiOPc, respectively. The output voltage sensing margins (i.e., photocurrent signal difference) of the hybrid organic-Si B, G, and R image sensor pixels presented results 17, 11, and 37% higher than those of conventional Si CISs. In addition, the hybrid organic-Si B, G, and R image sensor pixels could achieve an ideal aperture ratio (i.e., ~100%) compared with a Si CIS pixel using the backside illumination process (i.e., ~60%). Moreover, they may display a lower fabrication cost than image sensors because of the simple image sensor structure (i.e., hybrid organic-Si photodiode with four n-MOSFETs).

Two-dimensional van der Waals ferroelectric field-effect transistors toward nonvolatile memory and neuromorphic computing

With the gradual decline in Moore's law, traditional silicon-based technologies have encountered numerous challenges and limitations, prompting researchers to seek solutions. Two-dimensional (2D) van der Waals (vdWs) ferroelectric (Fe) field-effect transistors (FETs) (2D vdWs FeFETs) are devices that integrate emerging 2D vdWs ferroelectric materials into the transistor structures. In comparison with traditional complementary metal oxide semiconductor FETs (COMSFETs), they exhibit superior performance, including lower power consumption, higher switching speed, and improved stability. The vdWs FeFETs are anticipated to surpass the limits imposed by Moore's law, offering increased possibilities and opportunities for research and application in the field of nanoelectronics, particularly in nonvolatile memory (NVM) and neuromorphic computing (NMC). In this review, we summarize the recent research progress of vdWs FeFETs and elucidate their development origin, basic structure, and working mechanism. Furthermore, we explore the application of vdWs FeFETs in NVM, NMC, and large-scale arrays. Finally, we highlight the prominent challenges and future directions in this field.

Novel Design of Ripple Carry Adder using High Speed 12T Hybrid MOS Transistors

This paper designs and extends a high speed full adder using 12 MOS Transistors to a ripple carry adder (RCA). The proposed design reduces delay and is effective for Power Delay Product (PDP). Using both complementary MOSFET (CMOS) logic and complementary pass transistor logic(CPL), a new 6T XNOR full adder(FA) is created. CPL is used in the design for Carry and Sum logic in order to minimise circuit delay. The proposed work has a delay of 11.86 ps and a PDP of 0.368fj. By using a newly proposed single bit adder, a 4-bit Ripple Carry Adder(RCA) is designed with 1.2 v supply yielding a power of 572.063uw, delay 0.32ns and PDP 183.06 fj. The outcomes obtained are compared with existing models. For characterstics of speed and PDP, the proposed model outperforms existing models significantly. The circuit was designed in 90nm GPDK technology by using the CADENCE VIRTUOSO TOOL.

The impact of gate length, oxide dielectric materials, and oxide thickness on the GaNNT MOSFETs performance.

The expansion of the integrated circuit industry in recent years has been primarily propelled by the progressive growth of metal-oxide-semiconductor field effect transistors (MOSFETs). The device is employed as a rapid switch in computers advanced. The switching speed of MOSFETs is significantly influenced by the selection of gate length, oxide dielectric materials, and oxide thickness. Gallium nitride nanotubes (GaNNT) with remarkable stability in ambient conditions, making them a promising candidate for use as channel material in the forthcoming era of MOSFET technology. This study utilizes ab initio simulation to examine the device functionality of double-gate (DG) GaNNT MOSFETs sub- under the impact of gate length, oxide dielectric material, and oxide thickness. The findings suggest that enhancing the gate length and dielectric constant, as well as reducing the oxide thickness, can lead to significant improvements in the ratio of , subthreshold swing (SS), transconductance ( ), power dissipation (PDP), and delay time ( ). The enhancement is notably conspicuous when considering a channel length that is for devices of n-type. Hence, GaNNT demonstrates significant potential as a channel material in the advancement of complementary MOSFETs that are compatible with both n-type and p-type devices.

Analog Multiply-Accumulate Cell With Multi-Bit Resolution for All-Analog AI Inference Accelerators

Mixed-signal AI accelerators offer the possibility of higher energy efficiency for moderate resolution computations compared to their digital counterparts. All-analog implementations, where all operations are performed in the analog domain, can further improve this energy advantage. An energy efficient multiply-accumulate cell for all-analog neural layer processing macros is presented. The proposed analog two-quadrant multiplier circuit consists of two complementary MOSFETs where the pulse width modulated input activation is applied to the gates and the weight signal to the isolated back-gate. The analog multi-bit resolution weight is dynamically stored on a memory capacitor. The multiply-accumulate operation result is represented by charge accumulated on a summation line and drawn from or put onto a computation capacitance. Simulation results based on a 22 nm FD-SOI CMOS technology show that the cell consumes about 0.67 fJ for a circuit-level multiply-accumulate operation. An area efficiency of 166 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{12}$</tex-math> </inline-formula> MAC/s/mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^2$</tex-math> </inline-formula> is achieved.

A systematic study on complementary metal-oxide semiconductor technology (CMOS) and Internet of Things (IOT) for radioactive leakage detection in nuclear plant

Although nuclear power plants produce about 20% of India's power, the risk posed by radioactive leakage is considerable. Radiation leakage detection devices must be installed in all nuclear power plants to ensure that avoidable catastrophes never occur again and that the loss of human life is prevented. A safe atmosphere for inhabitants and workers may be ensured by keeping a consistent radiation level in all applications that use radioactive material. Complementary Metal-Oxide Semiconductor technology, or CMOS, uses complementary and symmetrical MOSFETS for logic-based functions in various applications, such as analog circuits (CMOS sensors). The Internet of Things (IoT) extends the power of the Internet beyond computing devices to a multitude of other things, processes, and environments. The main objective of this paper is to find a better and more creative solution for radioactive leakage detection techniques over present-day techniques. In this paper, the Authors aim to integrate CMOS and IOT applications for radioactive leakage detection methods on an industrial level. Within this paper, we have given brief descriptions of CMOS and IoT with their types, functions, methodology, and applications. CMOS is considered to be the most sophisticated and precise technology that can be employed to measure radiation leaks of all types (alpha rays, beta rays, gamma rays, and neutrons). With the help of IOT, massive disasters can be averted using complex alert systems. A well-coordinated combination of the two technologies has the potential to vastly increase leak detection potential and consistency. The study's major goal is to develop new and improved technology for detecting released radiation in the industry in order to obtain real-time information about the material leaked, as well as the location of the leak and the quantity of leakage that occurred, in order to reduce the danger of a natural catastrophe.

Ultrafast High Voltage Pulse Generator Based on Power MOSFETs Delay Push-pull Structure

In this paper, an ultrafast high voltage pulse generator based on power MOSFETs delay push-pull structure is designed. The two complementary power MOSFETs are connected in the push-pull circuit and driven by the low-power MOSFETs separately. The output ultrafast high-voltage pulse amplitude is +30 V ~ -200 V, and the front edge and back edge times of the pulse are 5 ns and 4 ns, respectively. The width and frequency of the output pulse are controlled by the external trigger input signal. The shortest output pulse width is 12 ns and the maximum operating frequency is 100 kHz while the load is 10 pF. The delay conduction method of power MOSFETs is helpful to reduce power dissipation and improve the reliability of the circuit at a high operating frequency.

The Power Optimization and an Area Efficient of Static RAM 1-Bit Cell using CMOS Novel Technologies

In order to meet all the expectations of consumers, today's technology is all equipped with large capacity memories. Additional factors include power consumption and delay, all of which are crucial in determining how well a gadget performs. Memory is an important factor of many widgets, and as devices get smaller, their size likewise gets less. Every computerized device, as a result, uses little power, and speed is of utmost importance. Since 6T Static Random Access Memory (SRAM) cells have advantages over other cells, the current scenario suggests that they are frequently employed for SRAM-based memory systems. Today's electronics businesses are primarily concerned with minimizing power consumption, with static and dynamic power dissipation being the two key considerations. Meeting customer demands, high bandwidth, low power, and fast-consuming storages are also required. The major objective of this research is to decrease the power dissipation of the SRAM. The main problem faced by the digital industry is the decrease of power and delay. By connecting two Complementary MOSFET inverters back-to-back, an SRAM cell can be set up in an easy and beneficial manner. This setup offers good noise immunity.

Complementary Transistors Based on Aligned Semiconducting Carbon Nanotube Arrays.

High-density semiconducting aligned carbon nanotube (A-CNT) arrays have been demonstrated with wafer-scale preparation of materials and have shown high performance in P-type field-effect transistors (FETs) and great potential for applications in future digital integrated circuits (ICs). However, high-performance N-type FETs (N-FETs) have not yet been implemented with A-CNTs, making development of complementary metal-oxide-semiconductor (CMOS) technology, a necessary component for modern digital ICs, impossible. In this work, we reveal the mechanism hindering the realization of A-CNT N-FETs contacted by low-work-function metals and develop corresponding solutions to promote the performance of N-FETs to that of P-type FETs (P-FETs). The fabricated scandium (Sc)-contacted A-CNT N-FET with a 100 nm gate length exhibits an on-state current (Ion) of 800 μA/μm and a peak transconductance (gm) of 250 μS/μm, representing the highest performance of CNT-based N-FETs to date. Moreover, CMOS technology has been developed to realize N- and P-FETs with symmetric high performance based on A-CNTs. The fabricated A-CNT CMOS FETs show electron and hole mobilities of 325 and 241 cm2 V-1 s-1, respectively, which are slightly higher than the corresponding values of Si CMOS transistors. Our scalable fabrication of A-CNT CMOS FETs with comparable electronic performance to Si CMOS will promote the application of CNT-based electronics in digital ICs.

Robust Anti-Ambipolar Behavior and Gate-Tunable Rectifying Effect in van der Waals p–n Junctions

Anti-ambipolar behavior has been observed in multilayer two-dimensional semiconductors and many p–n junctions. However, temperatures in the range of tens of kelvin are usually required, and there are gaps in the understanding of the underlying physics, most notably the roles of the space charge region and van der Waals (vdW) heterojunction. Here, we systematically investigate the unique transport and transfer characteristics of vertically stacked vdW contacted p-WSe2/n-SnS2 and p-WSe2/n-MoS2 junctions. Interestingly, robust anti-ambipolar behavior is observed at low and room temperature for both darkened and illuminated conditions. A peak-to-valley current ratio exceeding 104 and on-state gating field ranging from −0.3 × 106 to 0.57 × 106 V/cm are achieved at room temperature in darkness. Moreover, the rectifying effect and the type of majority charge carrier of the WSe2/SnS2 junction can be tuned by an electric gate. Robust Raman quenching over the whole interface induced by strong charge transfer is also observed. Based on an equivalent circuit model, a Poisson and drift-diffusion simulation, and experiments with local illumination, we highlight the role of the van der Waals heterojunction. We show that the observed unique anti-ambipolar behavior is due to the recombination of electrons and holes at the space charge region rather than carrier diffusion in the turned-off metal-oxide-semiconductor field-effect transistor (MOSFET). A larger vdW barrier and interface recombination at the vdW barrier are key to having a strong on/off ratio especially at room temperature. The p–n vdW heterostructure plays the roles of a complementary MOSFET connecting with a heterojunction diode, not only a ternary logic inverter but also a tunable multiple-gain amplifier in wide-range gating fields. The width of the middle logic plateau can reach 45 V in a WSe2/MoS2 junction.

(Invited) Achieving Lower Power Logic Using P-Type Metal Oxide Thin Film Transistors

Thin film transistors (TFTs) have enabled the active matrix displays that are a ubiquitous part of everyday life, from mobile phones and tablets through to desktop monitors and home televisions. They are used in the circuit at each pixel over the display as they can be fabricated for relatively low cost with excellent uniformity at low temperatures over large areas on glass substrates. These pixel circuits only require either n-channel or p-channel enhancement mode TFTs. However, there has long been a desire to integrate the display driver electronics onto the display panel as an alternative to connecting silicon-based integrated circuits using complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) to displays. More recently, there has been an increasing interest in producing other logic circuits using TFTs on glass and plastic substrates as this could enable a new generation of products with embedded electronics. However, both of these applications need low power logic circuits. CMOS is an inherently low power technology, but it requires both n-channel and p-channel transistors. Whilst this can be realised in silicon CMOS FETs, it has not yet been achieved using TFTs because it has proved difficult to realise both n-channel and p-channel devices using one material system at low cost. For example, hydrogenated amorphous silicon can be used to make reasonable n-type material but not p-type.Thin film oxide semiconductors such as amorphous indium gallium zinc oxide have been successfully commercialised in the pixel circuits of active matrix displays as they possess high field effect mobility, low threshold voltage, low off-state current and a high switching ratio. There is therefore a lot of interest in finding a suitable complementary p-type metal oxide thin film material to allow CMOS-type logic to be realised using this material system.Cuprous oxide is one such promising candidate material as the top of the valence band is dominated by states which form as a result of hybridisation of the completely filled Cu 3d orbitals and the O 2p orbitals. These hybridised states are less localised and have a higher dispersion with a resulting decrease in the effective mass of holes in these states and a higher carrier mobility. The results of an extensive study of this material shows that the grain structure is of critical importance with [100] oriented films resulting in a higher mobility. Furthermore, the impact of grain boundaries on conduction must be controlled. Although this allows TFTs with reasonable on-state current to be fabricated, it is found that there is a significant residual off-state current which is a result of electron accumulation in the channel. This is consistent with the high off-state current that has been observed widely in TFTs using p-type metal oxide thin film materials.The low off-state current in silicon MOSFETs means that the geometric transistor design in low power CMOS logic circuits only needs to focus on the effect of the on-state current in the p-channel and n-channel transistors. However, in TFTs, the much larger off-state current also becomes important as it can end up being a significant parameter when calculating the power consumption of CMOS logic circuits. An alternative geometric design parameter for TFT logic circuits is presented. This compares the maximum switching current with the static currents allowing optimisation based on both the noise margin and static power consumption. The result is improved performance of TFT-based CMOS logic circuits using the n- and p-type thin film oxide semiconductors that are currently available.

Power and Noise Reduction of High-Frequency Variable Gain Amplifier

This work illustrates the design of the cell-based variable-gain amplifier (VGA) with less power consumption and improved noise margin. The variable gain amplifier is incorporated into the current wireless front-end modules. The body-bias technique in the n channel MOSFET (n-MOS) devices greatly aided in the power reduction of the cells. The device characteristics were fine-tuned to get better gain and bandwidth and reduced the supply voltage. This technique ultimately reduced the number of cell stages required to meet the expectation. The reduction of the supply voltage and the technology upscaling helped to improve the noise margin. The presented unit cell achieved accurate dB-linear characteristics across a wide tuning range, based on a unique gain control method with a combination of sub-threshold n-MOS and saturation n-MOS transistors as active loads. A 7-cell reconfigurable VGA is simulated in 0.18-[Formula: see text]m Complementary MOSFET technology to verify the concept. The simulation results showed that the bandwidth of the VGA is greater than 2.5[Formula: see text]GHz, while less than 0.78[Formula: see text]mW is consumed from a 1.5-V supply. A noise figure of 23.7[Formula: see text]dB is measured. Also, the VGA achieves a gain control range of 19[Formula: see text]dB with a gain error less than [Formula: see text][Formula: see text]dB or 26.3%. These results make the designed amplifier adequate for high-frequency applications.

Design and Analysis of CMOS Phase Lock Loop (PLL) Using VLSI Technology

Abstract: This paper proffers comparative research of Complementary MOSFET (CMOS) of the Phase Lock Loop (PPL) circuit. Our approach is based on hybrid design Phase Lock Loop (PLL) circuits combined in a single unit. A phase-locked loop (PLL) is used in space communication for synchronization purposes also very useful in time to digital converters and in instrumentation engineering. A phased lock loop (PLL) is a control system that makes an output signal whose frequency depends on the input phase difference. The phase detector takes the phase of an input signal and compares it with the phase procured from its output oscillator regulates the frequency of its oscillator to manage the phase matches. Different techniques like analogue and digital simulation with the help of mathematical/logical connections are found in Research to create the Phase Locked Loop (PLL). This limitation can be overcome by replicating the circuit block whose supply voltage is being reduced to manage the same throughout. This paper includes design features for low power phase-locked loop using Very-large-scale integration (VLSI) technology. The signal from the phase detector controls the oscillator in a feedback loop. As such: an operational device the PLL has a wide range of applications in computers sciences, telecommunication, and electronic system applications; we aim to design and examine the phase lock loop circuit in multiple technologies and examine their power capacity. By using the hybrid structure of NMOS and PMOS, here we have achieved the circuit of Phase Lock Loop (PLL) using VLSI technology. Keywords: Technology, CMOS, Phase lock loop, Micro wind, Voltage control oscillator, VLSI technology.

Filterless, Digital Class-BD Audio Amplifiers with Constant Common Mode Output Voltage

This paper presents new and original architectures and implementations of two filterless, open-loop digital Class-BD audio amplifiers with constant common mode (CM) output voltage. The first, low-power amplifier consists of four ultrahigh-current EL7158 pin drivers, the OUT pins of which form the H bridge. The drivers are controlled from the extended LBDD PWM modulator and have appropriately set voltage levels on the VL and VH pins. The second proposed amplifier consists of two cooperating H-bridge power stages (HBS) implemented on complementary MOSFET pairs and powered by two different voltages. Both HBSs are driven by four EL7158 pin drivers having appropriately adjusted voltage levels on the VL and VH pins and controlled by an extended LBDD PWM modulator. The hybrid 9 bit DPWM modulator uses a linearized Class-BD double-sided modulation scheme with pre-compensation, enabling the most faithful emulation of natural NBDD PWM and, thus, providing attractive spectral characteristics at the DM output. Basic SPICE simulations and experimental results of the proposed digital Class-BD amplifiers were compared with the conventional digital Class-BD amplifiers. The elimination of CM signals significantly contributes to the reduction in electromagnetic interference (EMI), particularly those produced on the cables connecting the loudspeaker to the HBS terminal. Proposed Class-BD amplifiers with original and new topologies, due to their simple design and easy control (no galvanic isolation of control signals and no floating bias power supplies), which generate no CM voltage and feature excellent DM performance, similar to conventional Class-BD amplifiers, are very attractive solutions for filterless Class-BD amplifiers.

Analyzing the impact of guard-ring on different dual-direction SCR by device simulation and TLP measurement

In this paper, the impact of the traditional interdigital DDSCR structure (TI-DDSCR) and the embedded DDSCR (EM-DDSCR) structure with and without P+ guard-ring is analyzed under the 0.5-μm complementary and double-diffused MOSFET (CDMOS) technology. In order to verify and predict the characteristics of those electrostatic discharge (ESD) protection devices, a transmission line pulse (TLP) testing system and device simulation platform have been used in this work. The test results show that the introduction of P + guard ring will increase the device forward trigger voltage (Vt1) by about 3 V and forward holding voltage (Vh) by 4-6 V, but has little effect on the forward failure current (It2). The reverse Vh is reduced by 4–6 V, while the reverse It2 depends on the layout geometry. Due to the different layout geometry, on the TI-DDSCR structure with P+ guard ring, their reverse It2 is reduced from 13.07A to 8.05A. On the contrary, on the EM-DDSCR with P+ guard ring, their reverse It2 increased from 6.55A to 10.10A.

Design and Analysis of CMOS Full Adder

This paper presents a comparative study of Complementary MOSFET (CMOS) full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. Full adder circuit is an essential component for designing of various digital systems. It is used for different applications such as Digital signal processor, microcontroller, microprocessor and data processing units (DSP). In most of these systems the adder lies in the critical path that determines the overall speed of the system. Full adder is mainly used in VLSI devices like microprocessor for computational purposes. The proposed full adder cell has low power consumption, better area efficiency. Recently, there have been massive research interests in this area due to the growing need for low-power and high-performance computing systems. Our aim is to design and compare the full adder circuit in various technologies and compare their power capacity. By using the hybrid structure of NMOS and PMOS, we have implemented the circuit of full adder.

Highly Sensitive DNA Detection Beyond the Debye Screening Length Using CMOS Field Effect Transistors

Field effect transistors are considered one of the key technologies to provide real-time and label-free biodetection. Direct detection in physiological solutions is, however, severely limited by the Debye charge-screening effect of the electrical double layer. Most measurements are therefore performed indirectly in diluted ionic-strength solutions. This study proposes a general technique based on modulation of the surface electric field of the CMOS (complementary metal oxide semiconductor) extended-gate field effect transistors (EGFETs) to investigate the screening effect on hybridized DNA (deoxyribonucleic acid) signals from 1 MHz to 15 MHz. The 32 EGFET sensor array exhibited a floating-gate potential change of 17.4 mV/log[DNA] from 1 fM to 100 pM with a near picomolar-level resolution and a response time below 8 minutes.

Power and delay analysis of different SRAM cell structures with different technology node

-Now adays Very Large-Scale Integration (VLSI) circuits have good or great demand. Because CMOS circuit design having less power consumption. Transistors on the chip is doubled every two years, according to Moore’s law. So, it means transistor size is decreasing. This leads to increase the chip density and decrease the device size. The write and read depending on the bitline and bitline bar discharging and charging. When design the memory in below 16 nm uses Fin Field effect Transistor (FinFET) technology instead of CMOS (Complementary metal oxide semiconductor field effect transistor). Because to avoid short channel effect. Comparing leakage power, dynamic power and static power at 90 nm technology and write delay, read delay at both 90 nm and 45 nm technology in nine transistors (9 t), eight transistor (8 t) and six transistor (6 t) sram cell.

Open-Loop Class-BD Audio Amplifiers with Balanced Common-Mode Output

This paper presents new architectures and implementations of original open-loop Class-BD audio amplifiers with balanced Common-Mode output. The output stage of each proposed amplifier includes the typical H-bridge with four MOSFETs and four additional MOSFET switches that balance and keep the Common-Mode output constant. The presented amplifiers employ the extended NBDD PWM or PSC PWM modulation scheme. When the output stage is built only on NMOSFET transistors, gate drivers require a floating power supply, using a self-boost charge pump with capacitive isolation of the control signal. The use of complementary MOSFETs in the output stage greatly simplifies gate control systems. The proposed amplifiers were compared to the typical Class-BD configuration, using the optimal NBDD modulation with respect to audio performance of the Differential-Mode (DM) and Common-Mode (CM) outputs. Basic SPICE simulations and experimental studies have shown that the proposed Class-BD amplifiers have similar audio performance to the prototype with the optimal NBDD modulation scheme, while at the same time having a balanced constant voltage CM output, thus eliminating the main contributor to radiation emission. As a result, the filtering of the DM output signals can be greatly simplified, while the filtering of the CM output signals can be theoretically eliminated. Practically, due to the timing errors added by the gate drivers, spikes are generated at the CM output, which are very easy to filter out by the reduced LC output filter, even at very low L.

Strengthened Complementary Metal-Oxide-Semiconductor Logic for Small-Band-Gap Semiconductor-Based High-Performance and Low-Power Application.

Silicon-based complementary metal-oxide-semiconductor (CMOS) has been the mainstream logic style for modern digital integrated circuits (ICs) for decades but will meet its performance limits soon. Extensive investigations have thus been carried out using other semiconductors, especially those with extremely high carrier mobility. However, these materials usually have small or even zero band gap, which leads inevitably to large leakage current or voltage loss in ICs based on these semiconductors. In this work, we propose and demonstrate a strengthened CMOS (SCMOS) logic style using modified field-effect transistors (FETs) to solve this problem, that is, to achieve high performance, utilizing the high carrier mobility in these materials, and to reduce the current leakage resulting from their small band gap. Conventional CMOS FETs are modified to have an asymmetric structure where an additional assistant gate is introduced near the drain to further lower the potential barrier in on-state and to increase the barrier in off-state. SCMOS ICs are constructed using these modified asymmetric CMOS FETs, which demonstrate perfect rail-to-rail output with negligible voltage loss and 3 orders of magnitude suppression of the static power consumption and an operating speed similar to or even higher than that of CMOS ICs. Here, SCMOS is demonstrated using carbon nanotubes, but, in principle, this logic style can be used in ICs based on any small-band-gap semiconductors to provide simultaneously high performance and low power consumption.