Analog Multiply-Accumulate Cell With Multi-Bit Resolution for All-Analog AI Inference Accelerators

Abstract

Mixed-signal AI accelerators offer the possibility of higher energy efficiency for moderate resolution computations compared to their digital counterparts. All-analog implementations, where all operations are performed in the analog domain, can further improve this energy advantage. An energy efficient multiply-accumulate cell for all-analog neural layer processing macros is presented. The proposed analog two-quadrant multiplier circuit consists of two complementary MOSFETs where the pulse width modulated input activation is applied to the gates and the weight signal to the isolated back-gate. The analog multi-bit resolution weight is dynamically stored on a memory capacitor. The multiply-accumulate operation result is represented by charge accumulated on a summation line and drawn from or put onto a computation capacitance. Simulation results based on a 22 nm FD-SOI CMOS technology show that the cell consumes about 0.67 fJ for a circuit-level multiply-accumulate operation. An area efficiency of 166 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{12}$</tex-math> </inline-formula> MAC/s/mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^2$</tex-math> </inline-formula> is achieved.