Complementary MOSFET Research Articles

Dual Metal/High-k Gate-Last Complementary Metal–Oxide–Semiconductor Field-Effect Transistor with SiBN Film and Characteristic Behavior In Sub-1-nm Equivalent Oxide Thickness

For the first time, dual metal/high-k gate-last complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) with low-dielectric-constant-material offset spacers and several gate oxide thicknesses were fabricated to improve CMOSFETs characteristics. Improvements of 23 aF/µm in parasitic capacitances were confirmed with a low-dielectric-constant material, and drive current improvements were also achieved with a thin gate oxide. The drive currents at 100 nA/µm off leakages in n-type metal–oxide–semiconductor (NMOS) were improved from 830 to 950 µA/µm and that in p-type metal–oxide–semiconductor (PMOS) were from 405 to 450 µA/µm with a reduction in gate oxide thickness. The thin gate oxide in PMOS was thinner than that in NMOS and the gate leakage was increased. However the gate leakage did not affect the off leakage below a gate length of about 44 nm. On the basis of this result, in these gate-last CMOSFETs, it is concluded that the transistors have potential for further reduction of the equivalent oxide thickness without an increase in off leakages at short gate lengths for high off leakage CMOSFETs. For low off leakage CMOSFETs, the optimization of wet process condition is needed to prevent the reduction of the 2 nm HfO2 thickness in PMOS during a wet process.

Preparation of Epoxy/Organoclay Nanocomposites for Electrical Insulating Material Using an Ultrasonicator

In this paper, we discuss design considerations for an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a lateral asymmetric channel (LAC) doping profile. We employed a 0.35 <TEX>${\mu}M$</TEX> standard complementary MOSFET process for fabrication of the devices. The gates to the LAC doping overlap lengths were 0.5, 1.0, and 1.5 <TEX>${\mu}M$</TEX>. The drain current (<TEX>$I_{ON}$</TEX>), transconductance (<TEX>$g_m$</TEX>), substrate current (<TEX>$I_{SUB}$</TEX>), drain to source leakage current (<TEX>$I_{OFF}$</TEX>), and channel-hot-electron (CHE) reliability characteristics were taken into account for optimum device design. The LAC devices with shorter overlap lengths demonstrated improved <TEX>$I_{ON}$</TEX> and <TEX>$g_m$</TEX> characteristics. On the other hand, the LAC devices with longer overlap lengths demonstrated improved CHE degradation and <TEX>$I_{OFF}$</TEX> characteristics.

Metal Schottky Source/Drain Technology for Ultrathin Silicon-on-Thin-Box Metal Oxide Semiconductor Field Effect Transistors

This paper reports novel, non-epitaxial raised source/drain (S/D) approaches to decrease the parasitic external resistance in complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) fabricated on ultrathin silicon on insulator (UTSOI). This technique utilizes a metal Schottky S/D process with dopant segregation. Selectively formed NiSi2 with dopant segregation fabricated by laser-spike annealing (LSA) significantly lowered effective Shottky-barrier height and, thereby, lowered contact resistance (ρc). Satisfying the requirements of UTSOI MOSFETs in the 32-nm node for low stand-by power (LSTP) application, external parasitic resistance was reduced to 140 (NMOS) and 350 (PMOS) Ω µm. Our results show that ρc is an important component of parasitic resistance in terms of improving device performance of UTSOI MOSFETs.

Metal Schottky Source/Drain Technology for Ultrathin Silicon-on-Thin-Box Metal Oxide Semiconductor Field Effect Transistors

This paper reports novel, non-epitaxial raised source/drain (S/D) approaches to decrease the parasitic external resistance in complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) fabricated on ultrathin silicon on insulator (UTSOI). This technique utilizes a metal Schottky S/D process with dopant segregation. Selectively formed NiSi2 with dopant segregation fabricated by laser-spike annealing (LSA) significantly lowered effective Shottky-barrier height and, thereby, lowered contact resistance (ρc). Satisfying the requirements of UTSOI MOSFETs in the 32-nm node for low stand-by power (LSTP) application, external parasitic resistance was reduced to 140 (NMOS) and 350 (PMOS) Ω µm. Our results show that ρc is an important component of parasitic resistance in terms of improving device performance of UTSOI MOSFETs.

Investigation of n-Type Pentacene Based MOS Diodes with Ultra-Thin Metal Interface Layer

In order to realize stable n-type characteristics of pentacene for applying to the organic complementary metal-oxide-semiconductor field-effect transistors (CMOS), we have fabricated pentacene based MOS diodes using ultra-thin Yb layer such as 0.5-3nm between gate insulator and pentacene. From the results of capacitance-voltage (C-V) measurements, excellent n-type C-V characteristics of the devices with 1 and 2nm-thick Yb were observed even though the devices were measured in air. These results suggested that the n-type semiconductor characteristics of pentacene are able to be improved by the thin Yb interfacial layer. Furthermore, the improved n-type characteristics of pentacene will enable the fabrication of flexible complementary logic circuits utilizing one kind organic semiconductor.

ダイオードクランプ形線形増幅回路の回生特性と電子負荷装置への応用

This paper presents operating characteristics of a diode-clamped linear amplifier (DCLA) in regenerative-operating conditions. The DCLA consists of series-connected MOSFETs, series-connected dc power supplies, and clamping diodes. The circuit configuration is similar to that in a diode-clamped multilevel inverter. The DCLA uses complementary MOSFETs. One of the series-connected MOSFETs is only operates in the active state, while the other MOSFETs are in that on- or off- state. Thus, the DCLA is much smaller in the power loss than a conventional class-B amplifier. In addition, the DCLA enables the regeneration of the electric power from the ac terminals to the dc power supplies, when connected to a regenerative load. The power loss under a regenerative condition is theoretically derived and verified by using the experimental setup of the 12-series DCLA. As a result, the experimental setup have demonstrated that the loss in the DCLA in a regenerative operation is only 8% of the regenerative power.

Physics, Technology, and Modeling of Complementary Asymmetric MOSFETs

The physics, technology, and modeling of complementary asymmetric MOSFETs are reviewed and illustrated with statistically representative silicon data from a recent manufacturing implementation, in which the transistors for the secondary power supply voltage are offered in asymmetric and symmetric constructions. The in-depth analysis of the device physics of asymmetric transistors provides new insights into their physical operation and into the operation of transistors using halo implants in general. The variability, matching, and noise implications of using halo implants are also analyzed, concluding that both asymmetric and symmetric devices need to be offered for uncompromised circuit design. The challenges associated with the compact modeling the asymmetric transistors are also reviewed and illustrated. The preferred manufacturing implementation uses retrograde wells with no dopant fillers at the surface, while avoiding the drain-to-source punch-through by source-side-only halo implants. In addition to the known switching speed and maximum voltage gain advantages of the asymmetric transistors, this particular device architecture offers superior hot-carrier reliability and transistor design flexibility. The availability of retrograde wells enables construction of high-reliability complementary extended-drain MOSFETs for a third higher power supply voltage.

An Efficient Threshold Voltage Control in Complementary Metal–Oxide–Semiconductor Field Effect Transistor Using Spacer Stress Engineering

In this work, we have demonstrated an efficient method to control threshold voltage in complementary metal–oxide–semiconductor field effect transistor (CMOSFET) using spacer stress technology compatible with a very-large-scale integration (VLSI) process. Consequently, the threshold voltage of the device could be shifted by 180 mV for n-type FETs (n-FETs) with a tensile-stressed SiN spacer and by 20 mV for p-type FETs (p-FETs) with a compressively stressed oxide spacer. From a theoretical thermodynamics model as well as reported experimental data, we demonstrated that spacer stress could play an important role on threshold voltage control due to altering the diffusivities of dopants in silicon.

Sub-30-nm Complementary Metal–Oxide–Semiconductor Field-Effect Transistor with Pt-Incorporated Fully Ni-Silicide/SiON Gate Stack

We demonstrated an ideal scaling of inversion gate dielectric thickness (Tinv) without the decrease in the channel strain of a short-channel planar transistor using a Pt-incorporated fully Ni-silicide (Ni-FUSI)/SiON gate stack. We have achieved drive currents of 1.1/0.65 mA/µm at an off-leakage current of 50 nA/µm for the sub-30-nm n- and p-metal–oxide–semiconductor field effect transistors (MOSFETs). Because the decrease in gate length was larger than the Tinv scaling while maintaining a high drive current, the Ni-FUSI/SiON gate stack improved the intrinsic delay of the scaled inverter.

Effect of Carrier Transit Delay on Complementary Metal–Oxide–Semiconductor Switching Performance

The high-speed switching performance of a complementary metal–oxide–semiconductor field-effect transistor (CMOSFET) inverters is analyzed. It is found that the propagation delay of an inverter can no lomger be described by a DC-current-based estimate, but that the charging/discharging current is essential for the propagation delay prediction under high-frequency operation.

Atomic Layer Control for Suppressing Extrinsic Defects in Ultrathin SiON Gate Insulator of Advanced Complementary Metal–Oxide–Semiconductor Field-Effect Transistors

By measuring the minimum supply voltage for normal operation of test random access memories, we detected low-density extrinsic defects in silicon-oxynitride (SiON) gate insulators that were formed by state-of-the-art technologies. The density of the detected defects had a strong correlation with optical thickness dopt, which was ellipsometrically measured, regardless of the processing conditions of the SiON films. We propose to maintain the dopt above a threshold value of 1.7 nm to suppress the problems caused by the defects. The optimization of post nitridation annealing (PNA) condition is promising for meeting the criterion without sacrificing device performance. By elaborate investigations based on the Clausius–Mosotti relation, we found that the optical thickness of SiON films is approximately proportional to the atomic area density in the films. On the basis of this finding, we developed a model, which is an extension of the conventional analytical cell-based model, to figure out the physical process of the extrinsic-defect formation. The results analyzed using the model revealed that the extrinsic defects are formed in the SiON films in the case when the number of normal cells in a vertical arrangement becomes equal to or smaller than the threshold value of 3 or 4.

Modeling and characterization of a 5.2 GHz VCO for UWB applications in 0.13 μm CMOS process

This paper describes a 5.2 GHz voltage-controlled oscillator (VCO) as a key component in RF transceivers. The circuit includes a complementary cross-coupled MOSFET as a negative conductance, beside a tank circuit which consists of an optimal on-chip spiral inductor (L), and an accumulation mode MOS varactor (C(V)). A model for phase noise and figure merit is introduced and verified through simulation in a standard 0.13 μm CMOS process. The VCO core drew a 4.2 mA of current from a 1.2 V power supply and a phase noise of ?98.5 dBc/Hz at 1 MHz offset from the 5.2 GHz carrier was calculated. The whole performance of the circuit specifically the tuning range was found to be 26%.

Device Optimization of N-Channel MOSFETs with Lateral Asymmetric Channel Doping Profiles

In this paper, we discuss design considerations for an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a lateral asymmetric channel (LAC) doping profile. We employed a <TEX>$0.35\;{\mu}m$</TEX> standard complementary MOSFET process for fabrication of the devices. The gates to the LAC doping overlap lengths were 0.5, 1.0, and <TEX>$1.5\;{\mu}m$</TEX>. The drain current (<TEX>$I_{ON}$</TEX>), transconductance (<TEX>$g_m$</TEX>), substrate current (<TEX>$i_{SUB}$</TEX>), drain to source leakage current (<TEX>$i_{OFF}$</TEX>), and channel-hot-electron (CHE) reliability characteristics were taken into account for optimum device design. The LAC devices with shorter overlap lengths demonstrated improved <TEX>$I_{ON}$</TEX> and <TEX>$g_m$</TEX> characteristics. On the other hand, the LAC devices with longer overlap lengths demonstrated improved CHE degradation and <TEX>$I_{OFF}$</TEX> characteristics.

Mechanism and CHARM2 Evaluation of P-Channel Metal Oxide Semiconductor Threshold Voltage Drop during High Density Plasma Heat-up Process

Plasma damage during the plasma deposition process is one of the most critical device characteristic issues facing complementary metal oxide semiconductor field effect transistor (CMOSFET) technology. In this paper, the CHARM2 monitoring system is used to evaluate UV damage and plasma charging damage during a high density plasma chemical vapor deposition (HDP-CVD) heat-up process. As a result, the amount of UV damage and negative charging damage is increased as the HDP-CVD heat-up process source power is increased. The main cause of P-channel metal oxide semiconductor field effect transistor (PMOSFET) threshold voltage drop is UV photon facilitated gate oxide electron trapping at the gate oxide and substrate P-channel interface during the HDP-CVD heat-up process. In N-channel metal oxide semiconductor field effect transistor (NMOSFET), when negative gate voltage stress is increased, gate oxide energy bend is flattened. Electrons cannot be trapped at the gate oxide and substrate N-channel interface. Therefore, the NMOSFET threshold voltage is constant during the HDP-CVD heat-up plasma process.

Smart Gas Sensor and Noise Properties of Single ZnO Nanowire

A new zinc oxide nanowire (NW) gas sensor based on the commercially available 0.35 µm complementary metal–oxide–semiconductor (CMOS) process is developed. The smart gas sensor consists of a gas-sensing resistor and an interface circuit for resistance measurement. The single ZnO NW synthesized by the vapor–liquid–solid (VLS) process is utilized as the gas-sensing resistor. The interface circuit for the resistance measurement of the single ZnO NW is composed of a ring oscillator circuit, in which the oscillation period is optimized with regards to the ZnO NW resistance and external capacitance to accurately detect the resistance of the ZnO NW after exposure to the gas. Because the low-frequency noise contains information about the charge fluctuations which are important for determining the gas-sensing reliability, the low-frequency noise of the single ZnO NW at various gate voltages, source–drain voltages and resistances is systematically characterized and compared with those of CMOS field-effect transistors (FETs) and network carbon nanotubes (CNTs) resistor.

A p-Channel Metal–Oxide–Semiconductor Field-Effect Transistor Charge Pump for Low Supply Voltages

In this paper, we propose a positive two-phase p-channel metal–oxide–semiconductor field-effect transistor (PMOSFET) charge pump with two auxiliary clocks to boost the gate biases of the switching transistors for low-supply-voltage applications. Owing to the effective boosting of the overdrive voltage of the charge transfer transistors, the proposed four-stage charge pump has high driving capacity and achieves a voltage gain of more than 90% with no load at a supply voltage of 1 V. The proposed charge pump was implemented using 0.18 µm standard complementary metal–oxide–semiconductor field-effect transistor (CMOSFET) technology in an area of approximately 0.205 mm2. The measurement results agree well with the simulated data, such as the simulated and measured output voltages without load reaching 8.6 and 8.28 V at a supply voltage of 1.8 V, as well as those with a 60 µA loading current producing 6.2 and 6 V at a frequency of 10 MHz, respectively.

A Novel High Stop Band All Complementary MOSFET Switched-Capacitor Filter

Problem statement: Filters are widely used in various applications in cluding communications, electronics and biomedical engineering. The performance and size of the filter is of interest especially in chip implementation. A switc hed-capacitor low-pass filter was designed and simulated using a 0.18 µm 1P6M CMOS technology. Approach: This circuit design offered obvious advantages in increasing the stopband attenuation, reducing passband ripple and achieving accurate frequency response. Results: This circuit achieved 53 dB stop band attenuation, less than 0.1 dB passband ripple, a 5 KHz cut-off frequency, a 100 K Hz stopband frequency and consumes 6 mW from a 2 V power supply. Conclusion: The proposed design is very suitable for the reali zation of analog signal processing blocks in complementary MOSFET integrated circuits.

Study of a DC-Voltage Equalizing Circuit and a Zero-Sequence Voltage Control Method for a Diode-Clamped Linear Amplifier

This paper proposes a dc-voltage equalizing circuit for a diode-clamped linear amplifier (DCLA). The DCLA consists of series-connected complementary MOSFETs and diode clamping circuits, which has an experimental efficiency as high as 90% without switching operation. The DCLA requires a dc-voltage equalizing circuit to divide the dc voltage into several levels. The proposed dc-voltage equalizing circuit enables to use a diode rectifier with a smoothing capacitor as a power supply for the DCLA. Moreover, zero-sequence voltage control is proposed to improve efficiency of the DCLA. As a result, a prototype twelve-series DCLA demonstrates an experimental efficiency as high as 94.7%.

Semiconducting Nanowire Field-Effect Transistor Biomolecular Sensors

Recent studies have demonstrated the ability of semiconducting nanowire (NW) field-effect transistors (FETs) to serve as highly sensitive label-free sensors for biochemicals, including small molecules, proteins, and nucleic acids. The nanoscale confinement of the channel current in concert with the large-surface area-to-volume ratio enables charged molecules bound to the surface to effectively gate the device. Functionalization of the NW surface with specific receptors therefore enables direct electronic detection of particular molecules of interest. The original work in the field relied on NWs grown by the chemical vapor deposition method, which require hybrid bottom-up fabrication processes for device realization. The lack of reproducibility with these techniques and the associated inability to leverage the central advantage of complementary MOSFETs, namely, very large scale integration, have recently led a number of groups to create NW sensors using only traditional top-down fabrication techniques. In this paper, we focus primarily on these most recent studies and discuss necessary future studies as dictated by experimental and theoretical considerations.

Effects of Strained Silicon Layer on Nickel (Germano)silicide for Nanoscale Complementary Metal Oxide Semiconductor Field-Effect Transistor Device

The effects of a strained silicon layer on the thermal stability of nickel (germano)silicide for nanoscale complementary metal oxide semiconductor field-effect transistor (CMOSFET) devices are discussed in this study. Three different thicknesses, 5, 13, and 40 nm, of silicon layers on silicon germanium (SiGe) were prepared for this experiment. The effects of the silicidation rapid thermal annealing (RTA) temperature and postsilicidation annealing temperature for the different silicon layer thicknesses were studied. For comparison, a bulk silicon substrate and a SiGe substrate were also used. Silicides with the thin strained silicon layers (5 and 13 nm) on SiGe showed good thermal stability in this study. However, the other silicides using bulk silicon, 40-nm-thick silicon on SiGe, and the SiGe substrate underwent degradation due to silicide agglomeration during annealing. A SiO2 layer was found on the silicide using the SiGe substrate. In this study, several analysis methods such as four-point probe measurement, field-emission scanning electron microscopy (FE-SEM), atomic force microscopy (AFM), and Auger electron spectroscopy (AES) were used for detailed study.