An Efficient Threshold Voltage Control in Complementary Metal–Oxide–Semiconductor Field Effect Transistor Using Spacer Stress Engineering

Abstract

In this work, we have demonstrated an efficient method to control threshold voltage in complementary metal–oxide–semiconductor field effect transistor (CMOSFET) using spacer stress technology compatible with a very-large-scale integration (VLSI) process. Consequently, the threshold voltage of the device could be shifted by 180 mV for n-type FETs (n-FETs) with a tensile-stressed SiN spacer and by 20 mV for p-type FETs (p-FETs) with a compressively stressed oxide spacer. From a theoretical thermodynamics model as well as reported experimental data, we demonstrated that spacer stress could play an important role on threshold voltage control due to altering the diffusivities of dopants in silicon.