Mechanism and CHARM2 Evaluation of P-Channel Metal Oxide Semiconductor Threshold Voltage Drop during High Density Plasma Heat-up Process

Abstract

Plasma damage during the plasma deposition process is one of the most critical device characteristic issues facing complementary metal oxide semiconductor field effect transistor (CMOSFET) technology. In this paper, the CHARM2 monitoring system is used to evaluate UV damage and plasma charging damage during a high density plasma chemical vapor deposition (HDP-CVD) heat-up process. As a result, the amount of UV damage and negative charging damage is increased as the HDP-CVD heat-up process source power is increased. The main cause of P-channel metal oxide semiconductor field effect transistor (PMOSFET) threshold voltage drop is UV photon facilitated gate oxide electron trapping at the gate oxide and substrate P-channel interface during the HDP-CVD heat-up process. In N-channel metal oxide semiconductor field effect transistor (NMOSFET), when negative gate voltage stress is increased, gate oxide energy bend is flattened. Electrons cannot be trapped at the gate oxide and substrate N-channel interface. Therefore, the NMOSFET threshold voltage is constant during the HDP-CVD heat-up plasma process.