Compact MOSFET Model Research Articles

Compact modeling of the high temperature effect on the single event transient current generated by heavy ions in SOI 6T-SRAM

A temperature dependence analysis of the single event transient current induced by heavy ions irradiation is performed in the range of 300K to 500K on a 1μm SOI CMOS MOSFET standard 6T-SRAM cell. The Sentaurus TCAD mixed-mode numerical simulation showed a significant impact of the temperature on the current induced by the radiation and as a result, an increase of the 6T-SRAM sensitivity upon radiation. A SOI MOSFET compact model introduced in SPICE as a Verilog-A module reproducing the single event effects was developed. This model shows a very good agreement with the TCAD simulations results but with a drastic reduction of the simulation time. Furthermore this model could be extended to other circuits simulations. This result is of importance to allow for extensive circuit design studies which cannot be carried out with TCAD physical simulations.

An approach based on particle swarm computation to study the nanoscale DG MOSFET-based circuits

The analytical modeling of nanoscale Double-Gate MOSFETs (DG) requires generally several necessary simplifying assumptions to lead to compact expressions of current-voltage characteristics for nanoscale CMOS circuits design. Further, progress in the development, design and optimization of nanoscale devices necessarily require new theory and modeling tools in order to improve the accuracy and the computational time of circuits' simulators. In this paper, we propose a new particle swarm strategy to study the nanoscale CMOS circuits. The latter is based on the 2-D numerical Non-Equilibrium Green's Function (NEGF) simulation and a new extended long channel DG MOSFET compact model. Good agreement between our results and numerical simulations has been found. The developed model can also be incorporated into the nano-CMOS circuits' simulators to study CMOS-based devices without impact on the computational time and data storage.

Parameter set and data sampling strategy for accurate yet efficient statistical MOSFET compact model extraction

Abstract This paper presents an effective statistical compact modelling strategy that can precisely capture a statistical set of MOSFET characteristics into industrial strength statistical compact models. 3D simulation of large statistical sample of microscopically different devices is required for statistical compact model extraction when studying the impact of variability in next CMOS technology generations on circuit and system design. For a particular nominal device design the statistical 3D physical simulations needs two orders of magnitude more CPU time compared to conventional TCAD simulations. A data sampling strategy is presented to reduce the number of bias points in simulated device characteristics used as extraction targets for statistical compact model parameter extraction. We show that for a well balanced set of statistical compact model parameters carefully chosen small number of strategic bias points in the simulated I–V characteristics of each microscopically different transistor is sufficient to capture accurately the statistical device behaviour. The corresponding increase in the RMS error is below 1% compared to results from comprehensive bias point set. The impact of the slight reduction of the compact model accuracy on the accuracy of statistical circuit simulation has also been investigated.

A new integration-based procedure to separately extract series resistance and mobility degradation in MOSFETs

A new procedure is presented to separate and extract source-and-drain series resistance and mobility degradation factor parameters in MOSFET compact models. It also allows us to extract the device's channel conductance. The procedure is not based on fitting, but on directly calculating the three parameters by solving a system of three simultaneous equations. The equations represent the measured source-to-drain output resistance, obtained from the output characteristics, and its first and second integrals with respect to gate voltage. This method may be applied to a single device, measured in strong inversion as a function of gate voltage, at a small drain bias.

Benchmark tests on symmetry and continuity characteristics between BSIM4 and ULTRA-BULK

This paper presents the benchmark test results on the symmetry and continuity characteristics between BSIM4 from Berkeley and ULTRA-BULK from Peking University. It is shown that the industry standard model BSIM4 has a series of the shortcomings of the continuity and symmetry, such as the charge, high-order current derivatives, and the trans-capacitances while the latest advanced surface-potential based MOSFET compact model, ULTRA-BULK, demonstrates all necessary continuity and symmetry characteristics, which are very important for analog and RF circuit design.

Benchmark Tests for MOSFET Compact Models With Application to the PSP Model

This paper presents the results of several qualitative ldquobenchmarkrdquo tests that were used to verify the physical behavior of the PSP model and its usefulness for future generations of CMOS IC design. These include newly developed tests and new experimental data stemming from low-power, RF, mixed-signal, and analog applications of MOSFETs.

Non-Quasi-Static Carrier Dynamics of MOSFETs under Low-Voltage Operation

We analyze the carrier dynamics in MOSFETs under low-voltage operation. For this purpose the displacement (charging/discharging) current, induced during switching operations is studied experimentally and theoretically for a 90nm CMOS technology. It is found that the experimental transient characteristics can only be well reproduced in the circuit simulation of low voltage applications by considering the carrier-transit delay in the compact MOSFET model. Long carrier transit delay under the low voltage switching-on operation results in long duration of the displacement current flow. On the other hand, the switching-off characteristics are independent of the bias condition.

Symmetrically linearised charge-sheet model for extended temperature range

The symmetrically linearised charge-sheet model, which forms the core of the industry standard compact MOSFET model is extended to a wide temperature range by including partial impurity freeze-out. The new model is verified by comparison with the exact results and includes the original formulation as a special case corresponding to complete impurity ionisation.

Generic Carrier-Based Core Model for Undoped Four-Terminal Double-Gate MOSFETs Valid for Symmetric, Asymmetric, and Independent-Gate-Operation Modes

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A generic carrier-based core model for undoped four-terminal double-gate (DG) MOSFETs has been developed and is presented in this paper. The model is valid for symmetric, asymmetric, and independent-gate-operation modes. Based on the exact solution of the 1-D Poisson's equation in a general DG MOSFET configuration, a rigorous derivation of the drain–current equations from the Pao–Sah's double integral has been performed. By using the channel carriers as the intermediate variable, a very compact analytical drain–current expression can be obtained. The model is extensively verified by comparisons with a 2-D numerical simulator under a large number of biasing conditions. The concise mathematical formulation allows the unification of various DG models into a carrier-based core model for a compact DG MOSFET model development. </para>

A scalable advanced RF IC design-oriented MOSFET model

This article presents a validation of the EKV3 MOSFET compact model dedicated to the design of analogue/RF ICs using advanced CMOS technology. The EKV3 model is compared with DC, CV and RF measurements up to 20 GHz of a 110 nm CMOS technology. The scaling behaviour over a large range of channel lengths and bias conditions is presented. Long-channel devices show significant non-quasi static effects while in short-channel devices the parasitics modelling is critical. This is illustrated with Y-parameters and ft vs. ID in NMOS and PMOS devices, showing good overall RF modelling abilities of the EKV3 MOSFET model. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2008.

Non-quasi-static approach with surface-potential-based MOSFET model HiSIM for RF circuit simulations

We develop a non-quasi-static MOSFET compact model suitable for simulating RF circuits operating under GHz frequency. The model takes into account the carrier dynamics by incorporating the time delay for the carriers to form a channel. Both the time-domain and frequency-domain expressions are successfully derived from the same basic equation by using the proposed modeling methodology, and the consistency of the both representations are verified. The model accuracy in predicting transient currents is demonstrated by comparing with simulation results of a 2D device simulator. The developed NQS model is implemented into SPICE3f5 and achieves stable circuit simulations with only 3 % simulation time increase.

Electrical characterization of ISFETs

Methodology of electrical characterization of ISFETs has been described. It is based on a three-stage approach. First, electrical measurements of ISFET-like MOSFETs and extraction of basic parameters of the MOSFET compact model are performed. Next, mapping of the ISFET channel conductances and a number of other characteristic parameters is carried out using a semi-automatic testing setup. Finally, ISFET sensitivity to solution pH is evaluated. The methodology is applied to characterize ISFETs fabricated in the Institute of Electron Technology (IET).

Fundamentals, Computer Implementation and Applications of the Advanced Compact MOSFET (ACM) Model

In this study we introduce a new computer implementation of the advanced compact MOSFET (ACM) model. The core ACM model, its computer implementation and some simulation tests are presented.

A Compact Model for Valence-Band Electron Tunneling Current in Partially Depleted SOI MOSFETs

The valence-band electron (EVB) tunneling current in partially depleted silicon-on-insulator (SOI) MOSFETs increases as the gate oxide gets thinner and affects the dynamic behavior of devices and circuits. We present an engineering model of EVB tunneling current based on the surface-potential formulation. The new model is implemented in a SOI MOSFET compact model and is used to study the impact of EVB tunneling on circuit performance. Simulations of stacked logic gates show that the EVB tunneling current not only boosts circuit switching speed but also mitigates the history dependence of propagation delays

On gate leakage current partition for MOSFET compact model

Aggressive scaling of the gate-oxide thickness has made gate-tunneling current an essential aspect of MOSFET modeling and this leakage current density continues to increase for every process generation. Accurate compact models for gate-tunneling current and its source/drain partition are extremely critical to valid circuit performance in the 90nm technology or beyond. Gate current partition has been studied by several authors [Cao K, et al. “BSIM4 gate leakage model including source–drain partition,” in IEDM Tech. Dig., San Francisco, CA, Dec. 2000. p. 815–8; R. van Langevelde et al., Gate current: modeling, ΔL extraction and impact on RF performance, in IEDM Tech. Dig., Washington, DC, Dec. 2001. p. 289–92; Shih W-K, et al., “A general partition scheme for gate leakage current suitable for MOSFET compact models,” in IEDM Tech. Dig., Washington DC., Dec. 2001. p. 293–6]. In this paper, an insight on the common/difference of these different gate leakage current partition schemes into source/drain has been provided and the accuracy of BSIM4 [Cao K, et al. “BSIM4 gate leakage model including source–drain partition,” in IEDM Tech. Dig., San Francisco, CA, Dec. 2000. p. 815–8] partition scheme is confirmed with comparing to the new derived equation, which incorporates the gate current into the inhomogeneous term calculation.

Circuit level prediction of device performance degradation due to negative bias temperature stress

A circuit level methodology for predicting performance degradations due to negative bias temperature stress is developed in this paper. Degradation mechanism is discussed based on experimental observations. Then, models that consist of a threshold voltage shift and a drain current reduction are developed based on the degradation mechanism. The developed models are implemented into a compact MOSFET model so that we can directly link the local degradation of pMOSFETs’ electrical characteristics to the total circuit performances. The validity of the developed models is confirmed by the good agreement in simulated and measured results of I– V characteristics of pMOSFET in all the transistor working region before and after negative bias temperature stress. Then, circuit performance prediction is carried out for the stressed 199-stage ring oscillator on its waveform and oscillation frequency. Excellent agreements between the experimental results and predicted results are obtained.

Analytical Modeling of Output Conductance in Long-Channel Halo-Doped MOSFETs

In this paper, a detailed physical analysis and an analytical derivation of the degradation of the output resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> ) observed in relatively long-channel laterally nonuniformly doped devices with halo implants are presented. Two-dimensional device simulations were performed, and the simulations show that the channel can be split into two uniformly doped transistors in series for the purpose of analysis. The lower doped bulk transistor is on the source side, while the higher doped halo transistor is toward the drain end. Based on this two-transistor analysis, a simple R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> degradation model is derived for implementation in a MOSFET compact model

HiSIM2: Advanced MOSFET Model Valid for RF Circuit Simulation

The compact MOSFET model development trend leads to models based on the channel surface potential, allowing higher accuracy and a reduced number of model parameters. Among these, the Hiroshima University Semiconductor Technology Academic Research Center IGFET Model (HiSIM) solves the surface potentials with an efficient physically correct iteration procedure, thus avoiding additional approximations without any computer run-time penalty. It is further demonstrated that excellent model accuracy for higher-order phenomena, which is a prerequisite for accurate RF circuit simulation, is achieved by HiSIM without any new model parameters in addition to those for describing the current-voltage characteristics

A new analytic approximation to general diode equation

This paper presents a new analytic approximation to the general diode equation with the presence of a series resistance. Using exact first- and second-order derivatives and a modified Newton–Raphson formula, a concise analytic approximate solution is derived for the diode equation with the significant improvement on the accuracy and computation efficiency, thus it is very useful for users to implement the diode model and the inversion charge models in other advanced MOSFET compact models such as ACM, EKV and BSIM5 into the circuit simulators, e.g., SPICE for circuit simulation and analysis.

A compact and accurate MOSFET model with simple expressions for linear, saturation and sub-threshold regions

A compact channel-current model is proposed for the linear, saturation and sub-threshold regions of MOSFETs with eight parameters at the maximum. To derive new formulas both physically reasonable and analytically simple, the core part of the known theories and formulas including BSIM is carefully examined, and the comparison with the exact gradual model is made. A simple formula for the linear region is obtained considering the velocity saturation effect, the bias dependent mobility and the series resistance in the source and drain junctions. It is theoretically predicted and experimentally confirmed that the two new parameters in the denominator strongly depend on the channel length. Simple expressions are additionally advised for the saturation and the sub-threshold regions. By applying the model to a set of devices covering a wide range of channel length, the parameters are extracted, and good agreement between theory and measurement is demonstrated.