CNTFET Technology Research Articles

Design of Efficient Ternary Operators for Scrambling in CNTFET Technology

Digital computation using ternary logic allows compact and energy-efficient digital design due to the reduction in circuit interconnects and chip area. CNFET unique characteristic of scalable threshold voltage value by utilizing the CNTs of different chirality vectors makes it a suitable option to realize ternary logic designs. This work presents hardware-efficient and low-power ternary operators exclusively used for scrambling applications in crypto-algorithms. The proffered designs are based on multiplexing the output digits among various unary cycle operators as the input trits. Extensive HSPICE simulations are conducted using standard 32-nm CNFET Stanford model to calculate the performance parameters of the proposed circuits. The presented designs show a significant improvement in terms of average power consumption, component count and energy consumption as compared to earlier counterparts. Results for various proposed scrambling operators Sop3, Sop4 and Sop5 show about an average reduction in energy consumption of 80% as compared to previously presented scrambling operators. Moreover, the Monte Carlo simulation results reveal that the proposed designs are robust against the mismatches in the diameter of CNTs.

A Novel Approach for Analysis CNTFET Based Domino circuit in Nano-Scale Design

As semiconductor industries is developing day by day to meet the requirement of today’s world. As scaling of ICs day by day to introduce functionality of the device while fabrication more and more component which results in shorter the life of the battery operated device which has to be improved. Here in this article we have measured performance parameters like power consumption, UNG, Evaluation Delay, standby power and speed of various domino circuits provided for various inputs like 8 &16 input OR gate. When we compared power, delay, and PDP of different topologies of domino circuit design with the simulation results which is performed by using SPICE tool at 32nm CNTFET process technology with supply voltage 0.9V and 27⁰ C of temperature at 100 MHz. All the simulation results is done in CMOS & CNTFET technology, it is observed that saving of average power upto 90.46% with same delay, with improvement of 5.8 × Noise-immunity with scaling of technology.

Small-signal parameters extraction and noise analysis of CNTFETs

The use of carbon nanotube (CNT) field-effect transistors (FETs) in microwave circuit design requires an appropriate, immediate and efficient description of their performance. This work describes a technique to extract the parameters of an electrical equivalent circuit for CNTFETs. The equivalent circuit is used to model the dynamic and noise performance at low- and high-frequency of different CNTFET technologies, considering extrinsic and intrinsic device parameters as well as the contact resistance. The estimation of the contact resistance at the metal/CNTs interfaces is obtained from a Y-function based extraction method. The noise model includes four noise sources: thermal noise, thermal channel noise, shot channel noise and flicker noise. The proposed model is compared with a compact model calibrated to hysteresis-free experimental data from a high-frequency multi-tube (MT)-CNTFET technology. Additionally, it has been applied to experimental data from another fabricated MT-CNTFET technology. The comparison in both cases shows a good agreement between reference data (simulation and experimental) and results from the proposed model. Low- and high-frequency noise projections of the fabricated reference device are further studied. Noise results from both studied technologies show that shot noise mainly contributes to the total noise due to the presence of Schottky barriers at contacts and along the channel.

Two state-of-the-arts current-mode ternary full adders based on CNTFET Technology

Adder core respecting to its various applications in VLSI circuits and<br />systems is considered as the most critical building block in microprocessors,<br />digital signal processors and arithmetic operations. Novel designs of a low<br />power and complexity Current Mode 1-bit Full Adder cell based on<br />CNTFET technology has been presented in this paper. Three major parts<br />construct their structures; 1) the first part that converts current to voltage; 2)<br />threshold detectors (TD); and 3) parallel paths to convey the output currents<br />flow. Adjusting threshold voltages which are significant factor for setting<br />threshold detectors switching point has been achieved by means of CNTFET<br />technology. It would bring significant improvements in adjusting threshold<br />voltages, regarding to its unique characterizations. Simple design, less<br />transistor counts and static power dissipation and better performance<br />comparing previous designs could be considered as some advantages of the<br />novel designs.

Newly multiplexer-based quaternary half-adder and multiplier using CNTFETs

In recent decades, due to the problems with the use of MOSFET transistors in Nanoscale, various alternatives have been introduced. Among them, CNTFET transistors are much more attractive due to their structural and behavioral similarities to the MOSFET transistors. Besides, using binary logic has made some issues that can be solved by applying multiple-valued logic. CNTFETs are also more suitable than MOSFETs in MVL circuits since their threshold voltage can be changed through a change of nano diameter. In this article, newly quaternary half-adder and single-digit multiplier through applying CNTFET technology based on the newly decoder and multiplexer are presented. Simulation of proposed designs is done with Synopsys HSPICE using 32 nm Stanford compact model. The functional results indicate the correct and perfect operation of all designs. Also, compared to some recent designs in literature, obtained 81.34% and 74.07% improvement in PDP for the half-adder and the multiplier designed, respectively. The simulation results under various load capacitors, supply voltage, process variations, frequency, and temperature confirm the stable operation of proposed designs.

Techniques to Improve the Performance in the CNTFET-Based Analogue Circuit Design

In this paper we show how to improve the performance of electronic circuits, through a comparative study between analogue circuits based on CNTFET and the conventionally ones based on MOSFET in 32 nm technology. In particular we design and compare an amplifier in source and drain common configuration and a self-biased cascode current mirror, highlighting that the procedure can be easily applied to a current mirror and a cascode current mirror. We show how the use of CNTFETs improves the performance of all proposed circuits with regards to the pass band, gain and output resistance. The simulation results, carried out with the simulator Advanced Design System, allow us to define quantitatively the differences between CNTFET and MOS technology and the advantages of the first for analogue VLSI circuits.

Comments on “High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits”

In the above article [1] , R. A. Jaber et al. present the designs of ternary logic circuits based on CNTFET technology. The motivation for designing ternary gates is based on the following assumption quoted in the abstract: “Moreover, multi-valued logic (MVL) circuits provide notable improvements over binary circuits in terms of interconnect complexity, chip area, propagation delay, and energy consumption.”

Design of Ternary Logic and Arithmetic Circuits Using GNRFET

Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits. Compared to the conventional and other emerging device technologies, Graphene Nano Ribbon Field Effect Transistor (GNRFET) appears to be very promising for designing MVL logic gates and arithmetic circuits due to some exceptional electrical properties of the GNRFET, e.g., the ability to control the threshold voltage by changing the width of the GNR. Variation of the threshold voltage is one of the prescribed techniques to achieve multiple voltage levels to implement the MVL circuit. This paper introduces a design approach for ternary logic gates and circuits using MOS-type GNRFET. The designs of basic ternary logic gates like inverters, NAND, NOR, and ternary arithmetic circuits like the ternary decoder, 3:1 multiplexer, and ternary half-adder are demonstrated using GNRFET. A comparative analysis of the GNRFET based ternary logic gates and circuits and those based on the conventional CMOS and CNTFET technologies is performed using delay, total power, and power-delay-product (PDP) as the metrics. The simulation and analysis are performed using the H-SPICE tool with a GNRFET model available on the Nanohub website.

Design of 8T CNTFET SRAM for Ultra-Low Power Microelectronic Applications

At around 10nm, direct source to drain tunneling in COS-MOS technology constituting fundamental limitations that in turn hold back their suitability for modern electronic appliances chiefly as far as area, energy competency and performance. In advanced electronic appliances, memory constituents play a crucial part. Almost in every digital appliance, memory component is mostly preferred due to its unique potentiality to withhold information. Due to rapid technology advancements, architecture of SRAM is truly tested as far as delay, energy efficiency and stability. Traditional 6T memory unit experiences passage transistor conflict arises the contrast among read balance and write competence. The paper that proposed here contrasts the performance of distinctive CNTFET based 8T memory unit architectures like Traditional and Dual-Port with respect to write delay, read delay and power efficiency like static and dynamic. 8T SRAM bit cell is designed with 32nm CNTFET technology using HSPICE Tool. From the HSPICE simulation results, Dual-Port CNTFET SRAM has provide better read and write delays were reduced by ~8.8% and ~16.3%, static power and dynamic power by ~12.5% and ~42.2% respectively than conventional one.

A vedic mathematics based processor core for discrete wavelet transform using FinFET and CNTFET technology for biomedical signal processing

This paper presents a new design for the implementation of Vedic mathematics based discrete wavelet transform for biomedical signal processing. The design of the low power architecture using alternate devices is the background of the work. The DWT architecture consists of the adder, multiplier, Multiply Accumulate (MAC) unit and RAM or ROM to store the co-efficients. The existing Complementary Metal Oxide Semiconductor based design suffers from leakage. The proposed FinFET and CNTFET technology will overcome the problem faced in CMOS technology. The processor core of the system on chip (SoC) designed using Vedic mathematics sutras. The efficiency of Vedic mathematics and advances of low power VLSI is combined in this paper. The CNTFET design reduces the power by about 95% and has controllability of the threshold voltage. The design is carried out in 32 nm FinFET technologyThe design is mainly focused on the complete Processor Core block implemented using a MAC with a Vedic multiplier using FinFET technology. The experiments were carried out using Synopsis HSpice.

Design and Analysis of Low-Power Adiabatic Logic Circuits by Using CNTFET Technology

Miniaturization of semiconductor industries paved the way for rapid development in the field of digital electronics. In DSM range, power dissipation has become a major concern due to leakage currents; hence, researchers are continuously trying to evolve ways to mitigate this. Out of many such ways the use of carbon nanotube technology is a promising way to design low-power circuits, as carbon has a property of providing variable threshold voltage (VTH) in N-type transistors. Here simulation results confirm that CNTFET has better performance than MOS and FinFET technologies in low-power world. In this paper existing and proposed adiabatic logic is implemented by CNTFET technology at 32 nm in HSPICE by using Predictive Technology Model (PTM). Comparison of simulation results shows that proposed CNTFET-based ON–OFF-DCDB-PFAL adiabatic logic saves average power 94.33% in Buffer/NOT, 93.13% in NAND/AND, 93.14% in NOR/OR, 91.76% in XOR/XNOR when compared with 2N2N2P circuit at 10 MHz frequency.

A Comparison of CNTFET and CMOS Technology through the Design of a SRAM Cell

In this paper we propose the design of a SRAM cell, based both on CNTFET and CMOS technology, in order to compare them. The first design is based on a CNTFET model, already proposed by us, while for the second one we use the BSIM4 model of the ADS library. In particular the MOSFET parameters, obtained using an evolution of previous Berkeley Predictive Technology Model (BPTM), are improved by us through parametric simulations to obtain performance of the MOSFET model comparable to the CNTFET one. At last we present the comparison between the two considered technologies, showing quantitatively the improvements obtained with CNTFET technology.

A new twelve-transistor approximate 4:2 compressor in CNTFET technology

ABSTRACTPower consumption is a serious concern in the field of digital design. Reducing power supply voltage, power gating, transistor downscaling, voltage over scaling, applying modern technology and approximate computing are some candidate means in reducing power consumption. Among these candidates, approximate computing can generate a trade-off between accuracy and power-delay-area efficiency in error resilient applications. According to Moore’s law together with CMOS problems in nanoscale regime, modern technologies emerge to solve these problems. Among these recent technologies, CNTFET technology is considered as promising. As multiplication is frequently applied in multimedia processing, implementing efficient multipliers constitute critical. Compressors are fundamental elements in reduction tree multipliers and improve their efficiency, thus an improvement in multipliers’ performance. A new 12-transistor approximate 4:2 compressor is proposed here. This new appropriate compressor, in terms of area, power consumption, accuracy and reliability design, is more efficient than its existing counterparts.

Design and Simulation Study of Full Adder Circuit Based on CNTFET and CMOS Technology by ADS

In this paper we propose the design of a novel full adder circuit, based both on CNTFET and CMOS technology, in order to compare them. The proposed full adder circuit is based on NAND and NOT logic gates. For this reason we characterize NAND and NOT gates at different supply voltages and frequencies, for both technologies. The optimal results, obtained using Advanced Design System (ADS), are at 0.5 V and 50 GHz for CNTFET, while for CMOS technology at 3 V and 200 MHz. Moreover we present the comparison between the two considered technologies in term of velocity, delay and power delay product (PDP), showing quantitatively the improvements obtained with CNTFET technology.

Designing and Optimizing DNA Reversible Adders and Adder/Subtractors

The construction of new biological systems is a new field of biological science in which many fields of science, such as chemistry and engineering, are simultaneously applied. Reversible logic has shown its capabilities for DNA computing, quantum computing, low-power computing, and nano-technology. Due to its inherently reversible features, DNA technology can be used as a suitable alternative to traditional silicon technology to decrease power consumption. One area discussed in the context of DNA-based calculations is the design of DNA-based gates and circuits using related biochemical operations. The present study designs DNA-based reversible adder and subtractor circuits. Toffoli, Feynman, and Fredkin gates are used to demonstrate reversible DNA-based half adder, full adder, half adder/subtractor, full adder/subtractor, and switchable half adder/subtractor designs. An optimization method is used to optimize the proposed DNA-based circuits to have power and delay as low as possible. The novel circuits are then optimized in quantum merit criteria of quantum cost, constant inputs, garbage outputs, delay, and number of gates, using a combination of Toffoli and Feynman gates. The comparative results show that our proposed reversible DNA-based switchable half adder/subtractor is more optimized than existing circuit in terms of quantum merit criteria. For the comparison, the proposed full adder is implemented using CMOS and CNTFET technology as well.

Performance analysis and enhancement of 10-nm GAA CNTFET-based circuits in the presence of CNT-metal contact resistance

The gate-all-around (GAA) CNTFET is one of the most efficient types of CNTFETs which provides the conditions for scaling the technology to 10 nm and beyond, due to the extraordinary features of carbon nanotubes and the superior gate control through a high-k insulator over the CNT channel. However, the high CNT-metal contact resistance at the source/drain terminals can significantly degrade the device and circuit performance in CNTFET technology compared to what we have expected. In this study, first a comprehensive comparative assessment of performance and robustness of the gate-all-around CNTFET- and FinFET-based devices and circuits is performed. In the GAA CNTFET-based circuits the contact resistance can be defined as a series resistor at each contacted node of transistors. In addition, an effective circuit-level solution for improving the performance of GAA CNTFET-based circuits in the presence of contact resistance is proposed. In this approach, the contact lengths of the devices located on the critical path are increased to an effective value to reduce the contact resistance considerably and the other contact lengths remain minimum-sized. The results demonstrate that applying this solution significantly improves the speed, energy consumption and energy-delay product of GAA CNTFET-based circuits.

CNTFET-Based Design of Current Mirror in Comparison with MOS Technology

In this paper we present, through the design of a basic and a cascode current mirror, a comparison between CNTFET and MOS technology. For every simulation parameters of merit, such as relative error in reference current replication and small-signal output resistance, are evaluated in order to show the differences between CNTFET and MOS technology and the advantages of the first for analog VLSI circuits.

Electrical Characterization of Emerging Transistor Technologies: Issues and Challenges

Experimental results gained by various electrical characterization techniques are discussed and compared for a CNTFET technology, which suffers as almost all emerging technologies from traps in the gate oxide. Based on these results, it is highlighted that, contrary to common practice, a fast data acquisition technique is required to ensure a proper electrical device characterization in terms of 1) trap-free device characteristics, 2) reproducible experimental results, and 3) a consistent set of dc and small-signal (ac) characteristics. It is argued that a reasonable technology comparison among emerging technologies must be based on data fulfilling these criteria since trap-affected measurements distort the device behavior which can lead to wrong conclusions about the performance of a device such as the apparent linearity. A trap model capturing the aforementioned issues is briefly introduced. Moreover, the challenges of the electrical characterization of high-impedance devices are explored.

Ternary cyclic redundancy check by a new hardware-friendly ternary operator

This paper presents a new ternary operator for cyclic redundancy check in ternary logic with high hardware efficiency. It shows the essential properties of a ternary operator for calculating CRC. Gate-level implementation of CRC-16 is exemplified and comprehensively explained in this paper. Transistor-level realizations of the new and the previous operators are also given in full detail. This paper demonstrates that the employment of the proposed operator reduces hardware components such as the elimination of one entire operator in both transmitter and receiver sides in comparison with ternary SUM. In addition, simulation results by HSPICE and 32nm CNTFET technology shows about 20.6% energy reduction for one of the implementation methods of the proposed operator with respect to the previously presented one (CCW CYCLE). Furthermore, five fewer transistors are needed to design the proposed operator in contrast with both operators SUM and CCW.

A Comparison of CNTFET Models through the Design of a SRAM Cell

In this paper we present a comparison of CNTFET models through the design of a SRAM cell, in order to identify the one more easily implementable in simulation software. In particular we consider two models, the first, already proposed by us, and the Stanford-Source Virtual Carbon Nanotube Field-Effect Transistor model (VS-CNFET). The simulation results of the design of a SRAM cell structure in CNTFET technology, by using the two models, are shown highlighting the comparison in terms of performance, power dissipation and stability.