A vedic mathematics based processor core for discrete wavelet transform using FinFET and CNTFET technology for biomedical signal processing

Abstract

This paper presents a new design for the implementation of Vedic mathematics based discrete wavelet transform for biomedical signal processing. The design of the low power architecture using alternate devices is the background of the work. The DWT architecture consists of the adder, multiplier, Multiply Accumulate (MAC) unit and RAM or ROM to store the co-efficients. The existing Complementary Metal Oxide Semiconductor based design suffers from leakage. The proposed FinFET and CNTFET technology will overcome the problem faced in CMOS technology. The processor core of the system on chip (SoC) designed using Vedic mathematics sutras. The efficiency of Vedic mathematics and advances of low power VLSI is combined in this paper. The CNTFET design reduces the power by about 95% and has controllability of the threshold voltage. The design is carried out in 32 nm FinFET technologyThe design is mainly focused on the complete Processor Core block implemented using a MAC with a Vedic multiplier using FinFET technology. The experiments were carried out using Synopsis HSpice.