Design of 8T CNTFET SRAM for Ultra-Low Power Microelectronic Applications

Abstract

At around 10nm, direct source to drain tunneling in COS-MOS technology constituting fundamental limitations that in turn hold back their suitability for modern electronic appliances chiefly as far as area, energy competency and performance. In advanced electronic appliances, memory constituents play a crucial part. Almost in every digital appliance, memory component is mostly preferred due to its unique potentiality to withhold information. Due to rapid technology advancements, architecture of SRAM is truly tested as far as delay, energy efficiency and stability. Traditional 6T memory unit experiences passage transistor conflict arises the contrast among read balance and write competence. The paper that proposed here contrasts the performance of distinctive CNTFET based 8T memory unit architectures like Traditional and Dual-Port with respect to write delay, read delay and power efficiency like static and dynamic. 8T SRAM bit cell is designed with 32nm CNTFET technology using HSPICE Tool. From the HSPICE simulation results, Dual-Port CNTFET SRAM has provide better read and write delays were reduced by ~8.8% and ~16.3%, static power and dynamic power by ~12.5% and ~42.2% respectively than conventional one.