CMOS Technique Research Articles

Design and Analysis of High Performance FinFET-Based Linear Feedback Shift Register for Cryptography Applications

Nowadays, all the elements of our surrounding is occupied by electronics. Electronics occupies major role on our day today life. Electronics device integration on a single chip enhances performance in terms of speed, low-power circuits, and area. Integration of VLSI provides better scalability and reliability. This research paper focused on the implementation of Linear feedback shift registers (LFSR) using FinFET techniques at the layout level for various applications, including cryptography. FinFETs are highlighted as a replacement for CMOS technology, offering advantages such as improved performance in terms of speed, low-power circuits, and area. Linear feedback shift registers are commonly used in digital systems and cryptography for generating pseudo-random sequences. The use of FinFET technology in the layout level suggests an interest in exploring advanced semiconductor technologies to enhance the performance of these circuits. The paper appears to cover different design methods of LFSRs, which could include aspects like circuit optimization, power efficiency, and reliability. The integration of electronics on a single chip, particularly with FinFET technology, is noted for its potential to provide better scalability and reliability. The first architecture is created using bulk CMOS techniques; whereas the second is constructed using two fin FinFET LFSRs. Using the Microwind designing tool, the third technique is developed with a 3-fin FinFET LFSR. It provides a solution for a novel FinFET architecture that implements LFSR. When comparing CMOS and FinFET circuit designs for LFSR, the latter achieves superior performance in terms of area and power efficiency. An analysis is conducted on the design techniques and performance of CMOS LFSR, 2 fin FinFET based LFSR, and 3 fin FinFET. According to the experimental findings, the CMOS-based LFSR uses 1.243 mW of power; the FinFET-based LFSR uses 90.47 μW, and the two fin FinFET LFRS uses 0.254 mW.

A Defects Classification Algorithm for the Hybrid OBT–IDDQ Fault Diagnosis Technique in Analog CMOS Integrated Circuits

In this paper, a robust fault detection methodology for complex analog CMOS integrated filters is presented. It is based on combining the two types of testing methodologies, Oscillation-Based Testing (OBT) and IDDQ testing, i.e., measuring of the power-supply current ([Formula: see text]). The proposed methodology is applied to the Bi-quad Sallen–Key band-pass (BP) filter cell with relatively complex, two-stage, class-AB-output, operational amplifier (opamp) topology. The filter is custom designed targeting the 180-nm CMOS technology. Hundreds of time-domain simulations and analyses of the circuit output signal are performed in order to obtain the fault dictionary. The presented results show that the proposed hybrid OBT–IDDQ methodology is significantly more efficient in the defects coverage than any of the particular test methodologies alone. Subsequently, the specific algorithm for the defects classification is proposed. Based on the classification, certain degree of diagnosis of the individual defect, or a group of defects, can be achieved.

Design and Optimization of Reversible Arithmetic Unit Using Modified Gate Diffusion Input Logic

ABSTRACTIncreasing integration levels and demand for portability have made minimising the power consumption of circuits increasingly important for wide range of applications. Reversible logic is a low-power, low-loss design that can be utilised in low power CMOS, optical computing, nanotechnology, and quantum computing. Quantum machine learning Research is an area examines combining ideas from quantum computing and machine learning. In this paper, a new design of reversible logic-based arithmetic unit is demonstrated with CMOS and modified-GDI (MGDI) methodology for nanoscales using reversible gates. We provide a design for an optimized arithmetic unit, as well as some proposed methodologies for designing a reversible arithmetic unit with novel reversible gates, and compare them to existing circuits in terms of garbage output, constant input, number of reversible gates, and quantum cost, in this work. It can also be employed in Quantum computers due to its lower Quantum Cost and Garbage Output. Transistor-level implementations of the proposed arithmetic units are accomplished using Cadence Virtuoso tool GPDK 90 nm technology in combination with CMOS and MGDI techniques. Due to the optimization, the proposed arithmetic unit shows better performance in worst-case delay and power consumption than a comparable non-optimized Arithmetic Unit. According to the design and analysis of proposed Arithmetic Units. The proposed −1 design of the 4-bit Arithmetic Unit achieves optimisation by incorporating a reduced number of reversible gates and exhibiting a low quantum cost (12&40) using MGDI-FS. Similarly, the proposed −2 and 3 designs minimizes the number of transistors required, with a count of 80 and 120, and proposed −3 design, it eliminates the presence of constant inputs entirely using MGDI-FS.

Design and Optimization of 4-Bit Array Multiplier with Adiabatic Logic Using 65 nm CMOS Technologies

ABSTRACT This paper proposes a 4-bit array multiplier useful in the design of basically mixer circuit, which is highly involved in signal and image processing using an efficient low-power VLSI technique. The presented architecture is completely implemented adiabatic techniques in the Near Threshold Region, which optimize the product of propagation delay and power dissipation. Multiplier is the most frequently used element in many digital electronics applications. Depending on the applications, various types of multipliers emerge. With this technique, the total power dissipation, i.e. dynamic power dissipation as well as static power dissipation is less as compared to the conventional CMOS technique. The Near Threshold Adiabatic Logic (NTAL) technique is used with a single timevarying power supply which reduces the clock tree management and enhances the energy-saving capability. Simulation of the proposed design is done by Cadence virtuoso schematic editor with specter simulator on TSMC 65 nm technology node to verify the optimized result. Also comparing our result to conventional CMOS techniques with all the same design parameters, the result shows that power dissipation improvement of approximately 66.6%, 14.4%, and 64.6% with respect to varying frequency, supply voltage, and load capacitance with other parameters keep constant such as if the frequency is varying than capacitance load value is C load = 10 pF and V DD(max) = 1.2 V, similarly if the supply voltage is varying than capacitance load value is C load = 10 pF and frequency F = 4 GHz and if load capacitance is varying than frequency F = 4 GHz and supply voltage V DD(max) = 1.2 V.

A high-efficiency spaceborne processor for hybrid neural networks

Featuring with characteristics of convolutional neural network (CNN) and recurrent neural network (RNN), hybrid neural network (H-NN) has been widely applied within the field of remote sensing. In order to satisfy de mands of on-orbit processing that requires high throughput with restriction on power consumption, designing specific heterogeneous array processor therefore becomes one of the most effective ways fulfilling various tasks engaged in the above field. In this paper, a heterogeneous array architecture is proposed to support the hybrid neural network, based on the characteristics of various computation types in between different neural network module types and of dynamic computation burden among different layers. Firstly, a heterogeneous array structure consisting of different PE, PPE, RPE and LPE units is proposed, enabling strong flexibility and high throughput. Four types of operation units are used for operations of MAC, ReLU, pooling and nonlinear lookup-table. Secondly, a multi-level on-chip memory structure and access strategy supporting different access modes are proposed to reduce the bandwidth requirements of off-chip data access and to improve the computation efficiency. Thirdly, a management strategy of heterogeneous computing array is designed, which combines pipelining and parallel processing to support efficient mapping of different types of hybrid neural networks. The hybrid neural network processor based on 65 nm CMOS technique has a peak throughput of up to 1.96 TOPS. The implementation on models of AlexNet, LRCN, VGG19-LSTM and CLDNN can achieve the throughput of 1.92 TOPS, 1.89 TOPS, 1.93 TOPS and 1.84 TOPS, respectively. Compared with the similar neural network processor that is based on the same technology, the throughput of AlexNet model is increased by 76.4%. The peak power consumption of a single processor core is 824mW, to which the power consumption restriction of on-orbit AI platform is satisfied.

Design and Optimization of A 4-bit Absolute-value Detector Using Half Adder and Comparator

In this paper, a design and optimization of a 4-bit absolute value detector is realized by using the CMOS technique, transmission gates, and the traditional comparator, which can compare the two positive input values all expressed in binary form. To optimize the overall performance of the absolute value detector, this paper chooses to minimize the number of transistors and simplifies the circuit through logical analysis. As for calculating the overall delay and energy consumption, critical path identification is also studied and analyzed in this paper. Based on the theory of path effort and path parasitic delay, the grid capacitance and resistance are introduced into the calculation of inverter ratios. To achieve various optimization objectives, this study also combines the grid size and power supply voltage scaling techniques to reduce the delay and energy of the circuit, and finally finds the minimum energy loss at a 1.5x delay. The overall delay and energy can be expressed by the multiple of the unit size inverter of that. As a compromise, a minimum delay of 1.5 times is selected to reduce energy consumption by 39.16 %.

Broadband ultrafast photogenerated carrier dynamics induced by intrinsic defects in <inline-formula><tex-math id="Z-20231102113631">\begin{document}$\boldsymbol\beta$\end{document}</tex-math><alternatives><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="21-20231173_Z-20231102113631.jpg"/><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="21-20231173_Z-20231102113631.png"/></alternatives></inline-formula>-Ga<sub>2</sub>O<sub>3</sub>

The ultra-wide bandgap semiconductor gallium oxide <i>β</i>-Ga<sub>2</sub>O<sub>3</sub> with enhanced resistance to the irradiation and temperature is favorable for high-power and high-temperature optoelectronic devices. <i>β</i>-Ga<sub>2</sub>O<sub>3</sub> also exhibits great potential applications in the field of integrated photonics because of its compatibility with the CMOS technique. However, a variety of intrinsic and extrinsic defects and trap states coexist in <i>β</i>-Ga<sub>2</sub>O<sub>3</sub>, including vacancies, interstitials, and impurity atoms. The defect-related carrier dynamics in <i>β</i>-Ga<sub>2</sub>O<sub>3</sub> not only adversely affect the optical and electrical properties, but also directly limit the performance of <i>β</i>-Ga<sub>2</sub>O<sub>3</sub> based devices. Therefore, a comprehensive understanding of the carrier transportation and relaxation dynamics induced by intrinsic defects is very important. Supercontinuum-probe spectroscopy can provide a fruitful information about the carrier relaxation processes in different recombination mechanisms, and thus becomes an effective way to study the defect dynamics. In this work, we study the dynamics of carrier trapping and recombination induced by intrinsic defects in pristine <i>β</i>-Ga<sub>2</sub>O<sub>3</sub> crystal by using wavelength-tunable ultrafast transient absorption spectroscopy. The broadband absorption spectra induced by the intrinsic defects are strongly dependent on the polarization of pump pulse and probe pulse. Particularly, two absorption peaks induced by the two defect states can be extracted from the transient absorption spectra by subtracting the absorption transients under two probe polarizations. The observed defect-induced absorption features are attributed to the optical transitions from the valence band to the different charge states of the intrinsic defects (such as gallium vacancy). The data are well explained by a proposed carrier capture model based on multi-level energies. Moreover, the hole capture rate is found to be much greater than that of the electron, and the absorption cross-section of the defect state is at least 10 times larger than that of free carrier. Our findings not only clarify the relationship between intrinsic defects and photogenerated carrier dynamics, but also show the importance in the application of <i>β</i>-Ga<sub>2</sub>O<sub>3</sub> crystals in ultrafast and broadband photonics.

DESIGN OF A 6T SRAM CELL WITH MINIMAL POWER USING CADENCE VIRTUOSO

It has proven challenging for VLSI designers to lower leakage power at the nanoscale level. This is because high- end gadgets, battery-operated portable pads, and other communication tools are in high demand. Memories are made up of static RAM and dynamic RAM. SRAM has had a significant impact on the worldwide VLSI market sinceit is preferred over DRAM because to its rapid read and write access times. Using a 6T static random access memory cell, this study's novel approach to lowering leakage current at various technologies has been put forth. To reduce the 6T SRAM cell leaking power, three source biasing techniques are used. At 45 nanometer and 90 nm technology nodes, the three techniques are NMOS diode clamping, PMOS diode clamping, and NMOS-PMOS diode clamping. The implementation of a 6T SRAM cell using the Multiple Threshold CMOS (MTCMOS) technique at 45nm technology is also emphasised in this article. Using the cadence virtuoso tool, the simulation is completed and different power dissipations are examined for 45 nm and 90 nm technologies, respectively, at supply voltages of 0.45 V and 0.9 V. Comparing PMOS clamping to the other two suggested techniques, an average power reduction of 82.19% was observed.

An Ultrasonic Energy Harvesting IC Providing Adjustable Bias Voltage for Pre-Charged CMUT.

Ultrasonic wireless power transmission (WPT) using pre-charged capacitive micromachined ultrasonic transducers (CMUT) is drawing great attention due to the easy integration of CMUT with CMOS techniques. Here, we present an integrated circuit (IC) that interfaces with a pre-charged CMUT device for ultrasonic energy harvesting. We implemented an adaptive high voltage charge pump (HVCP) in the proposed IC, which features low power, overvoltage stress (OVS) robustness, and a wide output range. The ultrasonic energy harvesting IC is fabricated in the 180 nm HV BCD process and occupies a 2 × 2.5 mm2 silicon area. The adaptive HVCP offers a 2× - 12× voltage conversion ratio (VCR), thereby providing a wide bias voltage range of 4 V-44 V for the pre-charged CMUT. Moreover, a VCR tunning finite state machine (FSM) implemented in the proposed IC can dynamically adjust the VCR to stabilize the HVCP output (i.e., the pre-charged CMUT bias voltage) to a target voltage in a closed-loop manner. Such a closed-loop control mechanism improves the tolerance of the proposed IC to the received power variation caused by misalignments, amount of transmitted power change, and/or load variation. Besides, the proposed ultrasonic energy harvesting IC has an average power consumption of 35 μW-554 μW corresponding to the HVCP output from 4 V-44 V. The CMUT device with a local surface acoustic intensity of 3.78 mW/mm2, which is well below the FDA limit for power flux (7.2 mW/mm2), can deliver sufficient power to the IC.

A 28-GHz wideband power amplifier with dual-pole tuning superposition technique in 55-nm RF CMOS

This paper presents a 28-GHz wideband power amplifier (PA) with the dual-pole tuning superposition technique for 5G applications in a 55-nm RF CMOS. The PA employs a four-stage pseudo-differential structure together with the two-way combining approach to enhance the power gain. Transmission-line transformer (TLT) matching networks are proposed in the PA for not only performing the impedance matching, but also tuning the peak gains of the four stages to two different pole frequencies. The dual-pole frequencies are eventually superposed to improve the bandwidth and gain. Meanwhile, techniques of capacitance neutralization, load-pulling, and power combination are adopted for power stages to improve the output power and efficiency significantly. Biased at the class-A mode by a supply voltage VDD of 1.5 V, the fabricated PA exhibites the measured peak small-signal gain (S21) of 21.9 dB and power gain (PG) of 20 dB at 28 GHz. The measured performances of saturated output power (Psat) of 15.4–16.8 dBm, output 1-dB compression point (OP1dB) of 12–13.5 dBm, and power added efficiency (PAEP1dB) of 11%–14.7% are achieved over the bandwidth of 24–30 GHz, featuring wideband linearity/PAE. The chip occupies a core area of 1.5 × 0.6 mm2.

Design and Leakage Power Optimization of 6T Static Random Access Memory Cell Using Cadence Virtuoso

Reduction of Leakage power at nano meter regime has become a challenging factor for VLSI designers. This is owing to the need for low-power, battery-powered portable pads, high-end gadgets and various communication devices. Memories are made up of Static RAM and Dynamic RAM. SRAM has had a tremendous impact on the global VLSI industry and is preferred over DRAM because of its low read and write access time. This research study proposes a new method has been proposed of 6T Static Random Access Memory cell to decrease the leakage current at various technologies. Three source biasing methods are used to minimize the 6T SRAM cell leakage power. The three methods are NMOS diode clamping, PMOS diode clamping and NMOS-PMOS diode clamping at 45 nm and 90 nm technology nodes. This paper also emphasizes on the implementation of 6T SRAM cell using Multiple Threshold CMOS (MTCMOS) technique at 45nm technology. The simulation is achieved and various power dissipations are analyzed at supply voltage of 0.9 V and 0.45 V for 90 nm and 45 nm technology respectively using cadence virtuoso tool. PMOS clamping has shown the reduction in an average power by 82.19% than compared to other two proposed techniques.

Optimization of Gate Voltage in Capacitive DC–DC Converters for Thermoelectric Energy Harvesting

This article presents a fully integrated charge pump with optimized gate voltages for energy harvesting applications. In this article, design tradeoffs of gate voltages in low input voltage capacitive dc–dc converter designs are discussed and analyzed. The analysis shows that these tradeoffs can result in an optimum point where power losses can be minimized. Hence, gate voltage optimization is proposed to improve the power conversion efficiency. To prove the concept, five- and three-stage charge pumps with optimized gate voltages are implemented with the 180-nm CMOS technique. Down to 0.12-/0.13-V startup voltages are achieved by the proposed five-/three-stages design correspondingly. Comparing it with a similar three-stage linear charge pump in previous state-of-the-art research, a 20% peak power conversion efficiency improvement is achieved by the proposed design under the same 0.18-V input voltage.

Design and Analysis of a Novel Low Complexity and Low Power Ping Lock Arbiter by using EGDI based CMOS Technique

Network-on-chip (NoC) provides solution to overcome the complications of the on-chip interconnect architecture in multi-core systems. It mainly consists of router, links and network interface. An essential component of on-chip router is an arbiter that significantly impacts the performance of the router. The arbiter should provide fast and fair arbitration when it is placed in Critical Path Delay (CPD) systems. The main aim of this research work is to design a novel arbiter for an effective network scheduler in complex real time applications. At the same time resource allocation and power consumption should be very low. Previously, a novel gate level Ping Lock Arbiter (PLA) is designed to overcome the limited fair arbitration in Improved Ping Pong Arbiter (IPPA) with less delay. But the chip size and power consumption are very high. To overcome this problem, an Effective Gate Diffusion Input (EGDI) logic-based CMOS scheme is used to design a novel Compact Ping Lock Arbiter (CPLA). The proposed CPLA is compared with the existing PLA based on static CMOS scheme. The comparison between the conventional and proposed arbiter is carried out to analyze the area, delay and power by using Tanner Tool 14.1 with 250nm and 45nm technology. The proposed CPLA is suitable for compact and smart applications with glitch free and fair arbitration. The proposed CPLA presents 41.2% reduction in total area consumption. It also provides 47.12% average Area and Power Product (APP) reduction when compared to the existing 4-bit PLA. Similarly, the proposed 8-bit CPLA shows 49.48% average APP product shrinkage when compared to conventional 8-bit PLA. For low power and area constraint applications, the proposed CPLA with EGDI is best in comparison to the static CMOS based ping lock round robin arbiter. Therefore, the results demonstrate that the proposed CPLA achieves low power and consumes less area than the existing ping lock arbiter.

A 14-Bit 3-GS/s DAC Achieving SFDR >63dB Up to 1.4GHz With Random Differential-Quad Switching Technique

This brief analyzes the data-dependent switching distortion and the image tone in the current steering digital-to-analog converter (DAC). A switching scheme called random differential-quad switching (RDQS) is presented. This RDQS technique adopts two pairs of differential switches and randomizes the selection of the two pairs. Thus the data-dependent switching distortion and the image tone caused by the mismatch between the two pairs of differential switches are disturbed. With the RDQS technique and a specially designed switching signal generator, a 14bit 3GS/s current-steering DAC is implemented in 40nm CMOS technique. Measurements show that this DAC achieves spurious free dynamic range over 63dB and suppresses the image tone by 15dB. This DAC occupies 0.9mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 190 mW at 1V/2.5V supply.

Performance Comparison of the Conventional CMOS and MTCMOS Digital Circuits and Their Simulation

This paper focuses on the design of the conventional CMOS digital circuits and the Multi-Threshold CMOS (MTCMOS) digital circuits, which perform the specific Boolean logic function, as well as the comparison between these designing techniques by their functionality and power consummation (dissipation). The leakage of currents in integrated circuits based on CMOS logic becomes quite significant when the complementary MOS transistors are the small-device geometries (small dimensions), and this effect imposes alternative techniques that enable the designing of CMOS digital circuits with low-power dissipation, even in standby mode. One of these techniques is the design of the CMOS digital circuits with multi-threshold voltage (MTCMOS), which enables the reduction of the leakage power dissipation, as a part of the overall power dissipation in CMOS logic. Two CMOS digital circuits are designed (2-input XNOR CMOS gate and the other one is the CMOS gate that performs a complex Boolean function) based on conventional CMOS technique and multi-threshold voltage CMOS technique, and their functionality and calculation of the average overall power dissipation are tested using the Computer-Aided Design (CAD). The methodology used to achieve low power dissipation in CMOS digital circuits (MTCMOS) will be an efficient method for reducing the overall dissipation, while the high speed performance will be maintained.

Broadband near infrared all-dielectric metasurface absorber

Here we present a broadband all-dielectric metasurface absorber, where elliptical nanohole arrays are entirely embedded into the doped device layer of silicon-on-insulator wafer. From the intraband carrier transitions, the device exhibits enhanced near infrared absorption with a 3-dB bandwidth ∼ 35.3 nm. By the method of detailed multipole decomposition, we find that magnetic dipole resonances predominantly contribute to the absorption enhancement; in addition, the large bandwidth is attributed to the superposition of multiple absorption peaks from the resonances. The absorber designed in this simple structure and compatible with the CMOS techniques is promising for the broadband photodetectors of Si and even Ge. Differently, for the Ge-based photodetectors, the photocarrier excitation originates from interband transitions.

Power Efficient Biquadratic Filter designing using OTA

Objectives: To present a power efficient Universal Biquad Operational Transconductance Amplifier circuit. Methods: OTA (operational transconductance amplifier) based Biquad filter is analyzed using three different simulated tools three different tools (CADENCE, XILINX, ORCAD and MATLAB tools) are used for designing the circuit. The 0.18mm CMOS technique is used using the Cadence tool for plan and reproduction. The same circuit has been implemented on ORCAD tool as well as Xilinx tool. Findings: The proposed Biquad filter improves the frequency response, power dissipation and provides vary of the KHN biquadratic filter circuits it uses minimum numbers of Operational Transconductance phenomenon Amplifier (OTA) to realize an equivalent. The assorted parameters specifically Center frequency, dcgain, Bandwidth, Power Dissipation and Quality issue are all electronically tunable. OTA based Biquad filter is simulated in CADENCE Virtuoso tool. Opamp-RC Biquad filter offers a bandwidth of 425 kHz, pass band gain of zero DB, whereas Gm-C measuring system based mostly filter offers 85MHz, passband gain of zero DB. Over-all power dissipation of the Biquad filter is 4.3mW with 1.8V DC Supply has basing current of 50mA with gracefully voltage 2.5v. by keeping the supply voltage, bias current and load capacitor as 2.5V, 50mA and 10pFrespectively, it has been seen that the power is reduced using the CADENCE virtuoso tool. Novelty : This study presents a Universal Biquadratic filter having less power dissipation. The circuit was optimized for gain, GBP, slew rate, areas, voltage offset, phase margin, power area etc. compared to all the previous filter circuits (OTA GMC filters, OTA type-C filters) designed with the help of OTA. Keywords: OTA; CMOS; CADENCE Virtuoso; Static Power; Dynamic Power; MOSFET

Comparative Analysis of the Design Techniques for Low Leakage SRAMs at 32nm

This paper presents a comprehensive overview of leakage reduction techniques prevailing in Static Random Access Memories (SRAMs) by classifying them in three categories namely latch, bitline and read port. The performance of the techniques are evaluated in terms of leakage reduction capability along with the impact on read performance and hold stability through extensive simulative investigations at 32 nm technology node by taking conventional SRAM cell as reference. Further, as SRAMs are susceptible to inter-die as well as intra-die process variations, the performance at different PVT corners is also captured to demonstrate the efficacy of each technique under PVT variations. It is found that among the techniques used for reducing latch leakages, Multi-threshold CMOS technique possess the highest leakage reduction capabilities followed by Drowsy mode and Substrate-bias techniques. The results also indicate that Negative word line technique is more effective at low supply voltages whereas the Leakage biased bitline technique is more effective at high supply voltages for reducing bitline leakages. Amongst the read port leakage reduction techniques, Stack-effect and Dynamic control of power supply rail techniques are capable of suppressing the leakages at high voltages whereas Virtual cell ground technique is more efficacious at low voltages. The impact of technology scaling on SRAM cell performance with leakage reduction techniques is also studied. For the sake of completeness, suggestions are put forward for adopting a particular technique to address leakages at latch, bitline and read port levels.

Design and testing of a reversible ALU by quantum cells automata electro-spin technology

Arithmetic logic unit (ALU), a core component of a processor, is one of the thrust areas of the current research. Presently, ALU is designed by transistor-based CMOS technique and its individual components are placed in different layers. The current design is affected by the limitations of Moore’s law and design complexity. At present, ‘Quantum cellular automata electro-spin (QCA-ES)’ technology is widely accepted technology as an alternative of ‘CMOS’ to minimize the above discussed problems. In this research paper, the design of a novel multilayer portable, dynamic, fault-tolerant, power-efficient, thermally stable reversible ALU is proposed which is explored through QCA-ES. All the arithmetic and logical components of ALU are separately placed in different layers. Area density, delay, fault tolerance and thermal stability are investigated. A specific type of gate, known as reversible gate (modified 3:3 ‘TSG’ gate), is used in this proposed design with QCA technology to get the optimized design ALU with low occupied area, complexity, delay and power dissipation. Investigation of a fault-free design and saturated amplitude level (of output) change with respect to temperature increment in the proposed device are also discussed in this paper. Not only the thermal stability (up to 6 k temperature) but also an investigation on cell complexity of the 100% fault-free (against multiple cell-omission, cell-displacement, cell-orientation change and extra cell deposition), multilayer nano-device is represented in this work. ‘QCA-Designer’ software is used in this research work to design and develop layout of the proposed components in quantum-field and find out the occupied area, delay and complexity of proposed design. ‘QCA-Pro’ software is used for getting the value of dissipated power.

Design and Optimization of Reversible Logic Based Magnitude Comparator Using Gate Diffusion Input Technique

The power optimization is one of the biggest challenging issues for designing of VLSI circuits within the advanced technology. The reversible logic is one among the best approaches for low power application. This logic has wide applications in the communication, nanotechnology, digital signal processing, computer graphics, optical computing, etc. In this paper, some proposed reversible magnitude comparator has been designed using the prevailing reversible gates and implemented using gate diffusion input (GDI) technique. The design methodologies are also proposed for the designing of N-bit comparator. The main objective of this paper is to design and implementation of reversible magnitude comparator using some proposed methods and compares them with the existing circuits in terms of constant input, garbage output, number of reversible gates, and quantum cost. The transistor implementations of the proposed comparators are done by the combination of CMOS and GDI technique in EDA Tanner tools. After the design and analysis of proposed comparators it has been found that the proposed-2 logic based 4-bit comparator has lowest quantum cost which is equal to 38 and the proposed-3 logic based 4-bit comparator has lowest constant input and garbage output which is equal to 8 and 13.