CMOS Technique Research Articles

A Synthesis-Based Bandwidth Enhancement Technique for CMOS Amplifiers: Theory and Design

A synthesis-based bandwidth enhancement technique for CMOS amplifiers/buffers is presented. It achieves bandwidth-enhancement ratio (BWER) of 4.84, close to a proven theoretical upper limit of 4.93 for passive network with balanced capacitive loads. By employing a step-by-step design methodology, the proposed technique can be applied to any load condition, which is characterized by the ratio between the load capacitance and the output capacitance of the transconductor cell. Time-domain behavior of the proposed technique is examined. Two prototype amplifier/buffer circuits are designed using lower order passive networks to save chip area and circuit complexity. The test chips are fabricated in a 0.18 μm CMOS process, and measurements verify the frequency- and time-domain analyses. The amplifier provides 18.5 dB gain and 28 GHz bandwidth, while consuming 52 mW power from a 1.8 V supply.

Design and implementation of float point multiplier in X-DSP

In order to meet the requirements on performance, power, area of float point multiplier in X-DSP, the architecture of X-DSP was studied, and the characteristics of all the instructions related to its float point multiplier were analyzed. A high-performance and low-power float point multiplier, which used Booth 2 encoding algorithm and 4∶2 compress tree structure and adopt a 4-stage pipeline structure, was designed and implemented. The floating-point multiplier was also synthesized by using design compiler with 0.13 μm CMOS technique of a third-party company. The results show that the frequency is 500 MHz, the area of the circuit is 67529.36 μm2, and the total circuit power consumption is 22.3424 mW.

Complementary Pass-Transistor Adiabatic Logic Using Dual Threshold CMOS Techniques

With rapid technology scaling down, the energy dissipation of nanometer CMOS circuits is becoming a major concern, because of the increasing sub-threshold leakage in nanometer CMOS processes. This paper introduces a dual threshold CMOS (DTCMOS) technique for CPAL (complementary pass-transistor adiabatic logic) circuits to reduce sub-threshold leakage dissipations. The method to size the transistors of the dual-threshold CPAL gates is also discussed. A full adder using dual-threshold CPAL circuits is realized using 45nm BSIM4 CMOS model. HSPICE simulation results show that leakage dissipations of the CPAL full adder with DTCMOS techniques are reduced compared with the basic CPAL one.

Fast Determination of Similarity Between Two Vectors by Means of Analog CMOS Technique

Fast Determination of Similarity Between Two Vectors by Means of Analog CMOS TechniqueIn this paper, an analog approach to determining a resemblance between two multidimensional vectors is proposed. As the resemblance measure, Euclidean distance is used. The main advantage of the presented method is a very high speed of the Euclidean-distance-measure calculations. The achieved high speed results from the fact that most of arithmetic operations needed to realize the calculations are carried out in parallel. This concerns the required operations of squaring a difference of two corresponding components of the compared vectors. Operating in a transconductane mode (voltage difference squaring transconductors) and a current mode (output square-root extracting circuit), our CMOS circuit is power saving. Its low-power operation results from the fact that sub-circuits of our calculator responsible for the squaring operations (a great number of them in case of large multidimensional vectors) consume no power in the absence of input signals. This takes place when corresponding components of the compared vectors are both equal to zero. The circuit also consumes a reasonably low amount of energy when processing (comparing) a different from zero input data (corresponding vector components). A simplified description of the applied differential squaring transconductors as well as the output current-mode square-root extraction circuit is given and a problem of good cooperation between them is discussed and proper solutions indicated. SPICE simulation results are shown to be in a good agreement with the theory presented.

Development of a Multi-Quantum-Well Spatial Light Modulator and its Nonlinear Electro-Optical Driving Circuit

A Multi-quantum-well (MQW) spatial light modulator (SLM) was developed and tested. The test results shows that CR could reach 1.7,the swing of driving voltage is 1.5 under the conditions of room temperature while the wavelength is 847.6nm,and the CR could reach 5.1,the swing of driving voltage is 3.2 under the conditions of the temperature of -15.4oC while the wavelength is 846nm. A programmable driving circuit is also developed to aim at this SLM. The chip of this driving circuit, with 64×64 array, adopted the 0.35µm CMOS technique. The test results show that, the resolution of driving voltage is alterable and could up to 256-level with only 65*65µm2 pixel estate. The driving voltage swing is from 0 to VDD. It could be flip-chip bounded with Multi-quantum-well (MQW) spatial light modulator (SLM). The driving circuit meets all the requirements of the Multi-quantum-well (MQW) spatial light modulator (SLM).

A curvature-compensated CMOS voltage reference using [formula omitted] characteristics

A novel technique for the design of very low temperature coefficient (TC) voltage references in a CMOS standard process is presented. The proposed circuit uses an all CMOS technique to generate a low TC voltage reference over a wide temperature range. A self-biased Vth (threshold voltage) generator circuit creates a voltage equal to the Vth of a CMOS transistor; this voltage is used to generate a current proportional to Vth2 that, when forced into another transistor, creates a voltage which presents a negative non-linear temperature coefficient. A voltage with a positive TC, which can be controlled by the aspect ratio of a pair of transistors, is generated by a current mirror asymmetrically degenerated with a high-poly resistor. A curvature correction, provided by a current proportional to Vth2, is used to modify the thermal behaviour of this positive TC voltage. By adding the positive and negative TCs voltages, a very stable reference voltage can be obtained. The circuit was designed to be implemented in a standard CMOS process (AMS 0.35μm), and simulated results indicate that a variation of only 2.5ppm/∘C is expected over the temperature range of 0–90∘C.

Design Issues of CMOS VCO for RF Transceivers

This paper describes CMOS VCO circuit design procedures and techniques for multi-band/multi-standard RF transceivers. The proposed techniques enable a 4 ㎓ CMOS VCO to satisfy all requirements for Quad-band GSM/EDGE and WCDMA standards by achieving a good trade-off among important specifications, phase noise, power consumption, modulation performance, and chip area efficiency. To meet the very stringent GSM T/Rx phase noise and wide frequency range specifications, the VCO utilizes bond-wire inductors with high-quality factor, an 8-bit coarse tune capbank for low VCO gain(30～50 ㎒/V) and an on-chip 2nd harmonic noise filter. The proposed VCO is implemented in 0.13 ㎛ CMOS technology. The measured tuning range is about 34 %(3.17 to 4.49 ㎓). The VCO exhibits a phase noise of －123 ㏈c/㎐ at 400 ㎑ offset and －145 dBc/㎐ at 3 ㎒ offset from a 900 ㎒ carrier after LO chain. The calculated figure of merit(FOM) is －183.5 ㏈c/㎐ at 3 ㎒ offset. This fully integrated VCO occupies 0.45×0.9 ㎟.

A New Loss Compensation Technique for CMOS Distributed Amplifiers

This brief presents a circuit technique to compensate for the metal and substrate loss of the on-chip transmission lines (TLs), and, consequently, to improve the gain flatness and bandwidth of CMOS distributed amplifiers (DAs). An eight-stage DA suitable for 40-Gb/s optical communication is devised and implemented in a 0.13-mum CMOS process. The DA achieves a flat gain of 10 dB from dc to 44 GHz with an input and output matching better than -8 dB. The measured noise figure varies from 2.5 to 7.5 dB with the amplifier's band. The proposed DA dissipates 103 mW from two 1-V and 1.2-V dc supplies.

A NOVEL CMOS RIPPLE COMPARATOR CELL USING THE GATE- DIFFUSION INPUT TECHNIQUE

In this paper a new implementation of CMOS ripple comparator cell using the Gate-Diffusion Input (GDI) technique is presented. The proposed design using this technique allows for the reduction of power consumption, propagation delay, and the area of digital circuits while maintaining low complexity of logical design. The performance comparison with standard CMOS and GDI logic design techniques is presented. These methods are compared with respect to the number of devices, PDP, and power dissipation. Simulation results confirm that the proposed cell can work at low supply voltage and dissipates low power.

Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power

This paper presents an ultra-low power circuit design methodology which combines the Multi-Threshold CMOS (MTCMOS) technique with quasi delay-insensitive (QDI) asynchronous logic, in order to solve the three major problems of synchronous MTCMOS circuits: (1) Sleep signal generation, (2) storage element data loss during sleep mode, and (3) sleep transistor sizing. In contrast to most power reduction methods that result in area overhead, the QDI asynchronous MTCMOS circuits are usually smaller than their original versions. Moreover, QDI circuits utilize handshaking protocols instead of clocks for circuit control, resulting in flexible timing requirements, which yields increased circuit robustness and allows for extreme supply voltage scaling to subthreshold region for further power reduction, without requiring any circuit modifications. This QDI asynchronous MTCMOS methodology is used to design a 4-stage pipelined 8-bit x 8-bit unsigned multiplier, which is then compared against the original QDI design (i.e., without incorporating MTCMOS) and its synchronous version. All designs use the IBM 8RF-DM 0.13 μm process. Results show 150x and 1.8x leakage power and active energy reductions on average in the QDI asynchronous MTCMOS design compared to the original QDI version, respectively.

Current monitoring circuit for fault detection in CMOS integrated circuit

This article presents a built-in current sensor (BICS), which detects faults using the current testing technique in CMOS integrated circuits. This circuit employs cross-coupled PMOS transistors, which are used as current comparators. The proposed circuit has a negligible impact on the performance of the circuit under test (CUT). In addition, no extra power dissipation and high-speed fault detection are achieved. It can be applied to deep sub-micron processes. The validity and effectiveness are verified through the HSPICE simulation on circuits with faults. The entire area of the test chip is 116×65 μm2. The BICS occupies only 41×17 μm2 of the area of the test chip. The area overhead of a BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix 0.35 μm 2-poly-4-metal N-well CMOS process.

Programmable Switched Capacitor Finite Impulse Response Filter with Circular Memory Implemented in CMOS 0.18 μm Technology

This paper presents a programmable multi-mode finite impulse response (FIR) filter implemented as switched capacitor (SC) technique in CMOS 0.18 μm technology. Intended application of the described circuit is in analog base-band filtering in GSM/WCDMA systems. The proposed filter features a regular structure that allows for elimination of some parasitic capacitances, thus significantly improving the filtering accuracy. Due to its modularity that allows for dividing the circuit into two separate sections, the circuit can be easily reconfigured to work as either infinite impulse response (IIR) or as finite impulse (FIR) filter. One of the key components that allows for this multi-mode operation is the proposed programmable and ultra low power multiphase clock circuit. The 24-taps filter for the sampling frequency of 30 MHz dissipates power of 4.5 mW from a 1.8 V supply.

Injection-Locked Clock Recovery Using a Multiplexed Oscillator for Half-Rate Data-Recovered Applications

An injection-locked clock recovery circuit (CRC) with quadrature outputs based on multiplexed oscillator is presented. The CRC can operate at a half-rate speed to provide an adequate locking range with reasonable jitter and power consumption because both clock edges sample the data waveforms. Implemented by 0.18-μm CMOS technique, experimental results demonstrate that it can achieve the phase noise of the recovered clock about -121.55 dBc/Hz at 100-kHz offset and -129.58 dBc/Hz at 1-MMz offset with ±25 MHz lock range, while operating at the input data rate of 1.55 Gb/s.

Hybridization of CMOS With CNT-Based Nano-Electromechanical Switch for Low Leakage and Robust Circuit Design

Exponential increase in leakage power has emerged as a major barrier to technology scaling. Existing circuit techniques for leakage reduction either suffer from reduced effectiveness at nanometer technologies or affect performance and gate-oxide reliability. In this paper, we propose application of a specific carbon nanotube (CNT)-based nano-electromechanical switch as a leakage-control structure in logic and memory circuits. In case of memory circuits, we demonstrate that the proposed hybridization can be employed to reduce both cell leakage and bitline leakage, thereby improving the read noise margin as well. Due to the unique electromechanical properties of CNTs, these switches have high current-carrying capacity, extremely low leakage current, and low operating voltages. Moreover, they can act as nonvolatile memory elements, which can be exploited for data retention of important registers and latches during power down. Simulation results for a set of benchmark circuits show that we can obtain several orders of magnitude improvement in leakage saving in logic circuits at iso-performance compared to existing multi-threshold CMOS technique. In memory circuits, simulations show reduction in standby leakage and reduction in bitline leakage compared with the best existing techniques.

A 10-Gb/s Inductorless CMOS Limiting Amplifier With Third-Order Interleaving Active Feedback

This paper presents an inductorless circuit technique for CMOS limiting amplifiers. By employing the third-order interleaving active feedback, the bandwidth of the proposed circuit can be effectively enhanced while maintaining a suppressed gain peaking within the frequency band. Using a standard 0.18-mum CMOS process, the limiting amplifier is implemented for 10-Gb/s broadband applications. Consuming a DC power of 189 mW from a 1.8-V supply voltage, the fabricated circuit exhibits a voltage gain of 42 dB and a -3-dB bandwidth of 9 GHz. With a 231-1 pseudo-random bit sequence at 10 Gb/s, the measured output swing and input sensitivity for a bit-error rate of 10-12 are 300 and 10 mVpp, respectively. Due to the absence of the spiral inductors, the chip size of the limiting amplifier including the pads is 0.68times0.8 mm2 where the active circuit area only occupies 0.32times0.6 mm2

Ultra-low voltage high-speed Schmitt trigger circuit in SOI MOSFET technology

This paper proposes a novel ultra-low voltage and high speed Schmitt trigger circuit designed in silicon-on-insulator (SOI) technology. The proposed circuit is designed using dynamic threshold MOS (DTMOS) technique and multi-threshold voltage CMOS (MT-CMOS) technique to reduce power consumption and accomplish high speed operation. The experiment shows the proposed Schmitt trigger circuit consumes 4.68µW at 0.7V power supply voltage and the circuit demonstrates the maximum switching speed of 170psec.

New trends on photodetectors

The working horse for the detection of photons is the photomultiplier tube (PMT) which has been a commercial product since 1936. It is an elaborated device but still, after 70 years, impressive improvements have recently been achieved. PMTs however have two severe draw backs: they are sensitive to magnetic fields and they are expensive because the complicated mechanical structure inside the vacuum container is mostly handmade. This initiated the search for alternative devices. Photon sensitive semiconductor devices (PIN-photodiodes, avalanche photodiodes and recently Geiger-mode avalanche photodiodes) have been developed and have already replaced PMTs in many fields of research and will gain more ground in the near future. Geiger-mode avalanche photodiodes have an especially high potential because they have high gain and need no or only a simple amplifier and they can be produced with a standard and cost effective CMOS technique. However, when very large areas have to be covered the cheapest device is still probably a gaseous photomultiplier. Detectors based on the so-called Gas Electron Multiplier (GEM) foils, which minimize the harmful ion feedback, have high gain and even so a very long lifetime.

Sharp Bending of On-Chip Silicon Bragg Cladding Waveguide With Light Guiding in Low Index Core Materials

A novel on-chip Bragg cladding waveguide is designed and fabricated using conventional CMOS techniques. This optical waveguide has a low refractive index core surrounded by high index-contrast cladding bilayers. Polysilicon (n=3.5) and silicon nitride (n=2.0) are used for high index-contrast Bragg layers, where index difference is as high as 1.5. Our simulation shows that sharp bending in low index core materials can be achieved, which is not possible using index guiding mechanism. Within our approach, various on-chip applications are expected such as optical integration, high power transmission, biosensor/microelectromechanical system and so on

A CMOS Built-In Current Sensor for IDDQ Testing

This paper presents a new built-in current sensor (BICS) that detects defects using the current testing technique in CMOS integrated circuits. The proposed circuit is a negligible impact on the performance of the circuit under test (CUT). In addition, no extra power dissipation and high-speed fault detection are achieved. It can be applicable in deep submicron process. The area overhead of the BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix 0.35 μm standard CMOS technology.

A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector

SUMMARY A clock and data recovery (CDR) circuit using a new halfrate wide-range phase detection technique has been developed. Unlike the conventional three-state phase detectors, the proposed detector is applicable to the Non-Return-to-Zero (NRZ) data stream and also has low jitter and wide capture range characteristics. The CDR circuit was implemented in a 0.35-µm N-well CMOS technique. Experimental results demonstrate that it can achieve the peak-to-peak jitter of the recovered clock and the retimed data about 120 ps and 170 ps, respectively, while operating at the input data rate of 1 Gb/s. The total power dissipation of the CDR is 64.8 mW for the