Abstract
This article presents a fully integrated charge pump with optimized gate voltages for energy harvesting applications. In this article, design tradeoffs of gate voltages in low input voltage capacitive dc–dc converter designs are discussed and analyzed. The analysis shows that these tradeoffs can result in an optimum point where power losses can be minimized. Hence, gate voltage optimization is proposed to improve the power conversion efficiency. To prove the concept, five- and three-stage charge pumps with optimized gate voltages are implemented with the 180-nm CMOS technique. Down to 0.12-/0.13-V startup voltages are achieved by the proposed five-/three-stages design correspondingly. Comparing it with a similar three-stage linear charge pump in previous state-of-the-art research, a 20% peak power conversion efficiency improvement is achieved by the proposed design under the same 0.18-V input voltage.
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More From: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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