CMOS Power Amplifier Research Articles

INCAPE23-Design of Class E CMOS Power Amplifier with Integrated Active Inductor for 5G Applications

This paper presents a design of class E power amplifier (PA) with integrated active inductor for 5G applications. A high Q-factor active inductor (AI) is proposed utilizing CMOS 0.18-µm technology. A Gyrator-C based is employed to realize an active inductor with a double cascode resistive feedback configuration. The biasing voltage of 1.21 V, current source of 0.5 mA and supply voltage of 2.5 V is used. In order to obtain high efficiency, the proposed AI is implemented in a class E power amplifier by replacing on of the spiral inductors. According to the simulation results, the proposed AI can reach a high Q-factor of 50,000 and an inductance of 2.03 nH at 3.5 GHz. The power added efficiency (PAE) of CMOS class E PA with integrated AI, according to simulation result, is 72 % at 3.5 GHz. The intended PA's PAE was dramatically raised by the class E AI that was built.

A 46% PAE, 2.4-GHz Two-Stage Class E Power Amplifier Utilizing CMOS 0.13-µm Technology

A wireless device with a long battery life and great sensitivity becomes difficult to develop since there is a huge demand for low-power, low-cost wireless gadgets. The power amplifier (PA) is the most crucial part of radio frequency (RF) transceivers because of its massive power consumption. Consequently, in order to minimize power loss, a very effective and low-power consumption PA is needed. In this paper, high efficiency two-stage CMOS PA designed in 0.13-μm process for 2.4 GHz IoT transmitter applications is presented. The driver stage and power stage are the two stages that make up the two-stage topology of the proposed CMOS PA. To attain high efficiency and great power gain, a class E PA is used at the power stage. The LC matching network at the output is used for harmonic rejection filter at 2.4 GHz with an additional parallel capacitor helps for better harmonic rejection. In addition, a layout has been successfully designed and optimized. All the components in the proposed PA are designed on-chip. The pre-layout and post-layout simulations have been conducted to verify the proposed PA's performance. The pre-layout simulation of the proposed PA can deliver 19.19 dBm output power and 45.2% PAE at 2.0 V power supply into a 50-Ω load. On the other hand, the proposed PA produced an output power of 17.33 dBm and 46% PAE, according to the results of the post-layout simulation with a similar power supply of 2.0 V. The chip area for the proposed layout design is 1.05 mm2.

Design Techniques for Wideband CMOS Power Amplifiers for Wireless Communications

In this study, we designed a wideband CMOS power amplifier to support multi-band and multi-standard wireless communications. First, an input matching technique through LC network and a wideband design technique using a low Q-factor transformer were proposed. In addition, a design technique was proposed to improve output matching using RC feedback. To verify the feasibility of the proposed design methodology for wideband CMOS power amplifiers, the designed power amplifier was fabricated using a 180 nm RFCMOS process. The size including all of the matching network and test pads was 1.38 × 0.90 mm2. In addition, the effectiveness of the proposed power amplifier was verified through the measured results using modulated signals of WCDMA, LTE, and 802.11n WLAN.

Ka-Band Three-Stacked CMOS Power Amplifier With LC Shunt-Feedback to Enhance Gain and Stability

Ka-Band Three-Stacked CMOS Power Amplifier With LC Shunt-Feedback to Enhance Gain and Stability

D-Band CMOS Power Amplifiers: Challenges, State-of-the-Art, Technological Limitations and Trends

To achieve ultra-high-speed wireless communications, millimeter-wave bands have emerged as bands of interest for these new applications. However, a technological breakthrough linked to power amplifiers has appeared. Indeed, working near the maximum oscillation frequency of the transistor leads to low intrinsic gain and poor efficiency for these devices. This paper presents an overview of sub-terahertz CMOS power amplifiers with a focus on gain enhancement techniques. The paper will also feature state-of-the-art D-Band CMOS power amplifier architectures. The goal is to present how the gain enhancement techniques are used in a complete architecture. Based on the three techniques and the state-of-the-art presented in the paper, a focus on three architectures is proposed. The aim is to highlight the benefits of each method in the design. The final part summarizes the paper and opens up future perspectives and trends identified through the paper.

The Design and Process Reliability Analysis of Millimeter Wave CMOS Power Amplifier with a Cold Mode MOSFET Linearization

A power amplifier design operating at 28 GHz for communication applications is presented in this paper. Analog predistorted technique is used to improve the linearity using a cold mode MOSFET linearizer. The paper reports +19.8 dBm of peak power at the output and power-added efficiency (PAE) of 17% is attained by the designed circuit. The 1-dB compression point linearity was +18.6 dBm. The adjacent channel power ratio (ACPR) simulations were performed for the different communication standards like 802_11n_40M, CDMA, IS-95, and 802_11n_20M. Design specification variations of the amplifier have been analyzed over five process corners and simulations were performed to validate compliance with standards and robustness of the designed circuit. Monte Carlo simulation were performed to assess the performance over statistical variability of PAE and power gain. It is believed that this linearization design and the verifications used are done for the first time on a 65-nm RFCMOS process.

A highly robust RF 65 nm CMOS power amplifier design using Quasi-Newton control algorithm for wireless system

This article reports a novel robust approach towards CMOS power amplifier (PA) using Quasi-newton (QN) control algorithm in 65 nm CMOS process which provides best performance parameters over redundant wide bandwidth ranging from 2.4 to 16.4 GHz frequency band. Each stage are designed and optimized using QN algorithm to get desired goals such as high linearity, small group delay variations and high PAE across the entire frequency band of interest. Moreover, pole-zeros compensation technique is adopted and derived to get better stability of the proposed PA. The simulation and measurement results of PA achieved a small signal power gain of 10.5–16.8 dB with input return loss of better than 10 dB over the frequency band of 2.4 GHz to 16.4 GHz. A small group delay variation of ±58 ps over full frequency band of operation is achieved by optimizing the design parametric analysis. It is also observed that within the frequency of 6.5 to 14.6 GHz, an excellent small group delay variation of only ±11 ps is achieved and this is due to stage-2 tuning compensation technique. It also demonstrates the achieved input power in 1 dB compression points are −3.1 to 4.3 dBm, leading to maximum power added efficiency of 36.3%, respectively. The proposed PA consumes a lower DC power of 20.5 mW under supply voltage of 1.5. In addition, Process, voltage and temperature (PVT) analysis is executed at different conditions in order to achieve a robustness of the proposed PA over the entire band of operation.

CMOS Power Amplifier With Novel Transformer Power Combiner

A novel transformer combiner structure for wattlevel CMOS power amplifier design is presented in this letter. The proposed active skewered transformer (AST) utilizes the slab inductor as the secondary winding and overcomes the quality factor degradation issue when input cells are increased. Slab inductor has been previously used in the distributed active transformer (DAT) as the primary winding and achieved superior passive efficiency for the transformer combined CMOS power amplifier. However, we find that the slab inductor could be more beneficial as the secondary winding when we are aiming for higher output power from the CMOS power amplifier. The full-wave EM simulation has been performed and shows the advantage of AST over the conventional series-combining transformers (SCTs). Finally, a 2.4GHz CMOS power amplifier is designed based on the AST structure and fabricated in 0.18um CMOS process. The measured output power and power-added efficiency of the proposed power amplifier satisfying LTE specification with 5/20MHz bandwidth are recorded as 26.0/25.0dBm and 24.0/20.9%, respectively.

A Fully Integrated High Efficiency 2.4 GHz CMOS Power Amplifier with Mode Switching Scheme for WLAN Applications

A 3.3 V mode-switching RF CMOS power amplifier (PA) for WLAN applications is presented, which is integrated into a 55-nm bulk CMOS process. The proposed PA offers both static control and dynamic power control, allowing it to operate efficiently in both low-power and high-power modes. The pure low-power mode is achieved by reducing power cells, which are also used for linearization in high power mode. The low-power mode is achieved by reducing the number of power cells which are also used for linearization in the high-power mode. In the dynamic power control mode, the total AM–AM and AM–PM distortion is effectively compensated for by dynamically controlling the number of power cells and adjusting the matching input. The proposed PA achieves an output P1dB of 27.6 dBm with a PAE of 32.7% and an output P1dB of 17.7 dBm with a PAE of 10% in high-power and low-power modes, respectively. It is measured with an 802.11 n 64-quadrature-amplitude-modulation (MCS7) signal and shows a maximum average power of 19 dBm under an error-vector-magnitude (EVM) of −27 dB.

A Ka-Band CMOS Power Amplifier With OP1dB Improvement Employing a Diode-Connected Analog Linearizer

This paper presents a 30-36 GHz CMOS power amplifier (PA) with a diode-connected analog linearizer dedicated to improving the output power and power-added efficiency (PAE) at 1-dB output compression point (OP1dB). The proposed analog linearizer performs a gain expansion, simultaneously introducing little phase distortion. In addition, a design procedure of the matching network between the analog linearizer and PA is analyzed to mitigate the impact of impedance variation caused by the control voltage and input power. As a proof of concept, the circuit is fabricated in a 65-nm CMOS process with a 0.31 mm2 total area. Measured output power and PAE at OP1dB are > 13.4 dBm and > 12.4%, where maximum improvement of 2.2 dB and 5.9% is achieved at 31 GHz when the analog linearizer is active. The saturated output power of > 16.2 dBm is obtained with the saturated PAE of > 21%. Applying a single carrier 256-QAM signal with a bandwidth of 400 MHz and a peak-to-average power ratio (PAPR) of 10.4 dB, the PA with the proposed analog linearizer can achieve the adjacent channel power ratio (ACPR) of -34 dBc at the output power of 6 dBm.

A 5.3-GHz 30.1-dBm Fully Integrated CMOS Power Amplifier With High-Power Built-In Linearizer

A 5.3-GHz watt-level fully integrated CMOS power amplifier (PA) with a high-power built-in linearizer is presented in this letter. Utilizing a transformer (TF)-based 2-stage dual-radial power splitting/combining structure, the CMOS PA achieves watt-level output power. To enhance the linearity of the CMOS PA, a cascode cold-FET built-in linearizer which has high power capacity is developed. The CMOS PA achieves 30.1-dBm saturation output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {sat}}$ </tex-math></inline-formula> ), 27 dBm output 1-dB compression point ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$OP_{\mathrm {1dB}}$ </tex-math></inline-formula> ), 27.7 dB small signal gain, and 18% power added efficiency (PAE) at 5.3 GHz after linearization. Under the IEEE 802.11ac WLAN 20/80 MHz bandwidth 64/256 QAM OFDM modulated signals, the CMOS PA transmits linear output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {linear}}$ </tex-math></inline-formula> ) of 21/17 dBm with 5.6%/2.5% error vector magnitude (EVM), respectively. To our knowledge, the CMOS PA demonstrates the highest <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {linear}}$ </tex-math></inline-formula> and OP 1dB among other reported CMOS PAs around 5 GHz to date.

A Wide-Bandwidth PVT-Reconfigurable CMOS Power Amplifier with an Integrated Tunable-Output Impedance Matching Network

This paper proposes a wideband CMOS power amplifier (PA) with integrated digitally assisted wideband pre-distorter (DAWPD) and a transformer-integrated tunable-output impedance matching network. As a continuation of our previous research, which focused only on linearization tuning for wideband and PVT, this work emphasized improving the maximum output power, gain and PAE across the PVT variations while maintaining the linearity for a wide frequency bandwidth of 1 GHz. The DAWPD is employed at the driver stage to realize a pre-distorting characteristic for wideband linearization. The addition of the tunable-output impedance matching technique in this work provides stable output power, PAE and gain across the PVT variations, through which it improves the design's robustness, reliability and production yield. Fabricated in CMOS 130 nm with an 8-metal-layer process, the DAWPD-PA with tunable-output impedance matching can achieve an operating frequency bandwidth of 1 GHz from 1.7 to 2.7 GHz. The DAWPD-PA attained a maximum output power of 27 to 28 dBm with a peak PAE of 38.8 to 41.3%. The power gain achieved was 26.9 to 29.7 dB across the targeted frequencies. In addition, when measured with a 20 MHz LTE modulated signal, the DAWPD-PA achieved a linear output power and PAE of 24.0 to 25.1 dBm and 34.5 to 38.8% across the frequency, respectively. On top of that, in this study, the DAWPD-PA is proven to be resilient to process-voltage-temperature (PVT) variations, where it achieves stable performances via the utilization of the proposed tuning mechanisms, mainly contributed by the proposed transformer-integrated tunable-output impedance matching network.

A Wideband CMOS Power Amplifier With 52% Peak PAE Employing Resistive Shunt Feedback for Sub-6 GHz 5G Applications

This letter presents the design and implementation of a wideband power amplifier (PA) for sub-6 GHz 5G wireless applications. The PA employs a Class-B biased cascode topology with resistive shunt–shunt feedback for wideband response, good linearity, and simultaneous input and output matching. The design equations and stability considerations are laid out and are followed by experimental validation using both static and dynamic measurements. The chip prototype was fabricated in TSMC’s 65 nm CMOS technology. The PA operates from a 3.3 V supply and delivers a maximum power gain of 22.5 dB with a bandwidth of 2.17 GHz between 0.33 and 2.5 GHz, a peak output power of 21.5 dBm, and 52.4% power-added efficiency (PAE) at 1 GHz with >35% PAE over the operating frequency range. In the measurement of an orthogonal frequency-division multiplexing (OFDM) signal with 20 MHz modulation bandwidth and 10 dB peak-to-average power ratio (PAPR) at the average output power of 11 dBm around 1 GHz, EVM of −39 dB was achieved using memoryless polynomial-based digital predistortion (DPD).

Ka-Band Three-Stack CMOS Power Amplifier with Split Layout of External Gate Capacitor for 5G Applications

In this study, we designed a Ka-band two-stage differential power amplifier (PA) using a 65 nm RFCMOS process. To enhance the output power of the PA, a three-stack structure was utilized in the power stage, while the driver stage of the PA was designed with a common-source structure to minimize power consumption in the driver stage. The layout of an external gate capacitor for the stacked power stage was split to maximize the performance of the power transistor. With the proposed split layout of the external capacitor, gain, output power, and power-added efficiency (PAE) were improved. Additionally, a capacitive neutralization technique was applied to the power and driver stages to ensure the stability and enhance the gain of the PA. The measured P1dB and the saturation power were 22.0 dBm and 23.3 dBm, respectively, while the peak PAE was 27.8% at 28.5 GHz.

A 40% PAE and 34dBm Peak OIP3 CMOS Power Amplifier with Integrated Zero Power Consumption Phase Linearizer

In this paper, an Integrated Phase Linearizer (IPL) technique is designed to improve the linearity performance of a CMOS power amplifier (PA). The IPL is integrated at the gate of the PA so that the effect of the parasitic gate-to-source ([Formula: see text]) capacitance of the main transistor is compensated by the linearizer. Thus, it improves the 3rd-order intermodulation point (OIP3) without trading-off the power added efficiency (PAE). The proposed solution is designed and fabricated in an 180[Formula: see text]nm CMOS technology process consuming the chip area of 2.25[Formula: see text]mm2. At the operating frequency of 2.45[Formula: see text]GHz, it exhibits a gain of 11.14[Formula: see text]dB with unconditional stability characteristics from 1[Formula: see text]GHz to 10[Formula: see text]GHz. Biased quiescent current of 19.35[Formula: see text]mA, the IPL-PA delivers a maximum output power of 15.20[Formula: see text]dBm with 40.86% peak PAE, 34.91[Formula: see text]dBm of peak OIP3 and maximum power consumption of 63.65[Formula: see text]mW at 2.45[Formula: see text]GHz with supply voltage headroom of 1.8[Formula: see text]V. The proposed linearization scheme proved to be an excellent solution for low-power transceivers integration.

Design-Aware Parasitic-Aware Simulation Based Automation and Optimization of Highly Linear RF CMOS Power Amplifiers

In this paper, a parasitic-design-aware simulation-based design tool is proposed for highly linear RF power amplifiers. The main aim of the proposed tool is to speed up the design process of RF power amplifiers. In addition, it provides accurate final designs taking into consideration the effect of parasitic components of both active and passive devices. The proposed tool relies on the knowledge of designing highly linear RF power amplifiers. Both the optimization steps and design methodology are presented in this paper. The proposed tool is verified by designing a highly linear RF power amplifier at three different frequencies (7 GHz, 10 GHz, and 13 GHz) using 65 nm technology node. The results show that an OP1 dB higher than 18 dBm, gain/S21 higher than 7 dB, and OIP3 higher than 24 dBm at 6 dB back-off power can be obtained.

A 27-dBm, 0.92-GHz CMOS Power Amplifier With Mode Switching and a High-Q Compact Inductor (HQCI) Achieving a 30% Back-Off PAE

This brief reports a 0.92-GHz two-stage power amplifier (PA) in 130-nm CMOS process with improved back-off power efficiency and linearity. The two key techniques are: a switching mechanism for adaptive device sizing of the power stage, and a high-Q compact inductor (HQCI). The PA is designed to operate in low power (LP) mode and high power (HP) mode by using an NMOS pass transistor as a switch. The PA measures a peak output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{P}_{\mathrm{ out}}$ </tex-math></inline-formula> ) of 27 dBm with a peak power added efficiency (PAE) of 44%. The maximum linear output power reaches 21.5 dBm thanks to our unique HQCI-based output-matching network. At the back-off output power, a 10% increment in PAE is achieved by switching the size of the power stage with the MOS switch. Maximum <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{P}_{\mathrm{ out}}$ </tex-math></inline-formula> of 21.5 dBm is measured below −30 dBc ACLR and 4% EVM for the 16-QAM/20-MHz input modulated signal. The PA has an overall chip size of 1.382 x 1.425 mm2.

High PAE CMOS Power Amplifier With 44.4% FBW Using Superimposed Dual-Band Configuration and DGS Inductors

A two-stage 180-nm CMOS wideband (14–22 GHz) power amplifier (PA) with a superimposed staggered technique and defected-ground-structure (DGS) inductors is introduced, where a wideband peaking main stage is designed at the center frequency; then, a superimposed dual-band (SDB) driver stage is proposed to obtain the optimally flat gain response over the whole bandwidth (BW). Also, DGS inductors are used to enhance the power added efficiency (PAE) of the implemented PA by decreasing the matching circuits’ insertion losses. The proposed PA achieved a power gain of 12 dB at a total chip area of 0.564 mm2. Also, at the center frequency, it achieved a saturated output power of 16.6 dBm exhibiting the smallest reported amplitude-to-phase (AM-PM) distortion (2.1°) and group delay (GD) variations (±66 ps). Finally, it gives among the highest fractional bandwidth (FBW) (44.4%) and the PAE (18.7%) so far. Also, it achieves an error vector magnitude of −25 dB at 9.3-dBm output power for a 400-MHz 5G-NR signal.

Efficiency Enhancement of CMOS Power Amplifier for RF Applications

This paper presented a new structure for the CMOS power amplifiers as a more effective trend to amplify radio frequency (RF) signals compared to polar power amplifiers PA's by using envelope removal and restoration (EER) technique. Polar PA offers high-efficiency RF-modulated linear signal amplification. However, these amplifiers need high uniformity between the amplitude and phase of the modulated signals. The last translates promptly into higher energy consumption. Rather than deconstructing the quadrature signals into the combination of phase and amplitude signals, it is suggested that the CMOS quadrature power amplifier (QPA's) technique had been used to amplify RF signals immediately. The linearity, bandwidth, efficiency, and power consumption of the QPA's has been improved by separate amplitude and phase quadrature signals. The quadratic geometry architecture contains two bridges from modulated PA's that are able to treat negative or positive voltages, modulation, and RF-power bundling. The design of the new structure is compared with respect to parameters such as fundamental frequency, power gain, PAE, output power, technology or fabrication process, and number of stage transistors. Simulation results for PA's design using CMOS process show an effective quadrature model by a power-added-efficiency (PAE) of 78.413% at a maximum output power of 21.619dBm. The third intermodulation IDM3 is -49.2dBc at output power driven at frequency 2.4 GHz and input power greater than 20dBm. The amplitude and phase distortion has been obtained of 1.4 and 0.26 ᵒ/dB respectively at 50MHz of bandwidth for modulated signals.

MmWave Spatial–Temporal Single Harmonic Switching Transmitter Arrays for High Back-Off Beamforming Efficiency

This paper presents a spatial-temporal single harmonic switching (STHS) transmitter array architecture with enhanced efficiency in the power back-off (PBO) region. STHS is an electromagnetic and circuit co-designed and jointly optimized transmitter array that realizes beamforming and back-off power generation at the same time. The temporal dimension is originally added in STHS to achieve back-off efficiency enhancement, which can be combined with conventional power back-off enhancement methods such as Doherty amplifiers and envelope tracking. The design is validated through a simulation of a two-stage power amplifier in 65-nm CMOS at 77 GHz, which achieves a peak drain efficiency (DE) of 24.2%, a 22% DE at 3-dB PBO, 16% DE at 6-dB PBO, and 10.2% at 9-dB PBO. The efficiency exhibits a 57% improvement at 3-dB PBO, 100% improvement at 6-dB PBO, and 190% improvement at 9-dB PBO compared with class A/B amplifier.