A 27-dBm, 0.92-GHz CMOS Power Amplifier With Mode Switching and a High-Q Compact Inductor (HQCI) Achieving a 30% Back-Off PAE

Abstract

This brief reports a 0.92-GHz two-stage power amplifier (PA) in 130-nm CMOS process with improved back-off power efficiency and linearity. The two key techniques are: a switching mechanism for adaptive device sizing of the power stage, and a high-Q compact inductor (HQCI). The PA is designed to operate in low power (LP) mode and high power (HP) mode by using an NMOS pass transistor as a switch. The PA measures a peak output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{P}_{\mathrm{ out}}$ </tex-math></inline-formula> ) of 27 dBm with a peak power added efficiency (PAE) of 44%. The maximum linear output power reaches 21.5 dBm thanks to our unique HQCI-based output-matching network. At the back-off output power, a 10% increment in PAE is achieved by switching the size of the power stage with the MOS switch. Maximum <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{P}_{\mathrm{ out}}$ </tex-math></inline-formula> of 21.5 dBm is measured below −30 dBc ACLR and 4% EVM for the 16-QAM/20-MHz input modulated signal. The PA has an overall chip size of 1.382 x 1.425 mm2.