A highly robust RF 65 nm CMOS power amplifier design using Quasi-Newton control algorithm for wireless system

Abstract

This article reports a novel robust approach towards CMOS power amplifier (PA) using Quasi-newton (QN) control algorithm in 65 nm CMOS process which provides best performance parameters over redundant wide bandwidth ranging from 2.4 to 16.4 GHz frequency band. Each stage are designed and optimized using QN algorithm to get desired goals such as high linearity, small group delay variations and high PAE across the entire frequency band of interest. Moreover, pole-zeros compensation technique is adopted and derived to get better stability of the proposed PA. The simulation and measurement results of PA achieved a small signal power gain of 10.5–16.8 dB with input return loss of better than 10 dB over the frequency band of 2.4 GHz to 16.4 GHz. A small group delay variation of ±58 ps over full frequency band of operation is achieved by optimizing the design parametric analysis. It is also observed that within the frequency of 6.5 to 14.6 GHz, an excellent small group delay variation of only ±11 ps is achieved and this is due to stage-2 tuning compensation technique. It also demonstrates the achieved input power in 1 dB compression points are −3.1 to 4.3 dBm, leading to maximum power added efficiency of 36.3%, respectively. The proposed PA consumes a lower DC power of 20.5 mW under supply voltage of 1.5. In addition, Process, voltage and temperature (PVT) analysis is executed at different conditions in order to achieve a robustness of the proposed PA over the entire band of operation.