Chapter 3 - CMOS power amplifier design for wireless connectivity applications: A highly linear WLAN power amplifier in advanced SoC CMOS

Abstract

Modern wireless System-on-a-Chips (SoCs) for connectivity applications call for a highly integrated single chip solution at low cost and with a small form factor. This requires that the process node for most analog and RF blocks in transceivers should be scaled together with digital circuits, such as baseband and application processors. It becomes more challenging to design a highly linear and efficient power amplifier (PA) by using advanced CMOS technology for SoCs. This chapter describes a highly linear +28dBm class-AB PA in an advanced 32-nm SoC CMOS with flip-chip package for 2.4GHz WLAN SoC applications. It is designed with a relatively low 1.8V supply voltage, but achieves fairly high power-added efficiency and linearity simultaneously without digital pre-distortion linearization.