A 40% PAE and 34dBm Peak OIP3 CMOS Power Amplifier with Integrated Zero Power Consumption Phase Linearizer

Abstract

In this paper, an Integrated Phase Linearizer (IPL) technique is designed to improve the linearity performance of a CMOS power amplifier (PA). The IPL is integrated at the gate of the PA so that the effect of the parasitic gate-to-source ([Formula: see text]) capacitance of the main transistor is compensated by the linearizer. Thus, it improves the 3rd-order intermodulation point (OIP3) without trading-off the power added efficiency (PAE). The proposed solution is designed and fabricated in an 180[Formula: see text]nm CMOS technology process consuming the chip area of 2.25[Formula: see text]mm2. At the operating frequency of 2.45[Formula: see text]GHz, it exhibits a gain of 11.14[Formula: see text]dB with unconditional stability characteristics from 1[Formula: see text]GHz to 10[Formula: see text]GHz. Biased quiescent current of 19.35[Formula: see text]mA, the IPL-PA delivers a maximum output power of 15.20[Formula: see text]dBm with 40.86% peak PAE, 34.91[Formula: see text]dBm of peak OIP3 and maximum power consumption of 63.65[Formula: see text]mW at 2.45[Formula: see text]GHz with supply voltage headroom of 1.8[Formula: see text]V. The proposed linearization scheme proved to be an excellent solution for low-power transceivers integration.