A 5.3-GHz 30.1-dBm Fully Integrated CMOS Power Amplifier With High-Power Built-In Linearizer

Abstract

A 5.3-GHz watt-level fully integrated CMOS power amplifier (PA) with a high-power built-in linearizer is presented in this letter. Utilizing a transformer (TF)-based 2-stage dual-radial power splitting/combining structure, the CMOS PA achieves watt-level output power. To enhance the linearity of the CMOS PA, a cascode cold-FET built-in linearizer which has high power capacity is developed. The CMOS PA achieves 30.1-dBm saturation output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {sat}}$ </tex-math></inline-formula> ), 27 dBm output 1-dB compression point ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$OP_{\mathrm {1dB}}$ </tex-math></inline-formula> ), 27.7 dB small signal gain, and 18% power added efficiency (PAE) at 5.3 GHz after linearization. Under the IEEE 802.11ac WLAN 20/80 MHz bandwidth 64/256 QAM OFDM modulated signals, the CMOS PA transmits linear output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {linear}}$ </tex-math></inline-formula> ) of 21/17 dBm with 5.6%/2.5% error vector magnitude (EVM), respectively. To our knowledge, the CMOS PA demonstrates the highest <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {linear}}$ </tex-math></inline-formula> and OP 1dB among other reported CMOS PAs around 5 GHz to date.