CMOS Gate Research Articles

A fully integrated soft switched high frequency resonant DC‐DC voltage regulator

SummaryFully integrated 750‐MHz resonant voltage regulator is presented. Providing soft switching conditions for the transistors has prevented degradation of the converter efficiency at this high switching frequency. High switching frequency has reduced volume of the passive on‐chip components and thus increased the converter current density. Due to the limitations of the CMOS processes, control and gate drive circuits are designed to increase chip reliability. One of the major challenges of the fully integrated voltage regulators is the on‐chip inductor realization. Based on the mathematical models for inductance and resistance of spiral on‐chip inductor, the geometric dimensions of the employed inductor are optimally designed to have maximum quality factor and minimum chip area. The power switches are optimized to achieve maximum efficiency. All post layout parasitic elements of MOSFETs and metal routings including inductive effects are extracted using 3‐D EM simulation and finite element method for 0.18‐ m standard CMOS technology. Maximum output voltage ripple is 5.2% at maximum load current. Peak efficiency of the proposed on‐chip power supply is 82% when input/output voltage is 1.8 V/1.48 V and load current is 120 mA. Maximum value of the efficiency enhancement factor is 42% for output input/voltage of 1.8 V/0.55 V. Current density of the proposed converter is 574 mA/mm2. In the worst case, the load step causes an overvoltage/undervoltage smaller than 15.56% at the output voltage.

A self-control leakage-suppression block for low-power high-efficient static logic circuit design in 22 nm CMOS process

To maintain performance increase and reliability, power supply and threshold voltages will have to continually scale, in CMOS technology. With threshold voltage scaling and thinner gate-oxide thickness, sub-threshold and gate tunneling leakage powers are expected to become a significant portion of the total power in CMOS VLSI systems. A self-control leakage-suppression block (SCLSB) for leakage power reduction of static CMOS gates is proposed in this paper. The proposed SCLSB consists of two PMOS and two NMOS transistors that are located between pull-down network (PDN) and pull-up network (PUN). In any combination of input signals, one PMOS and one NMOS transistor of SCLSB turn on and the rest turn off, hence the resistance between the power supply voltage rail to the ground rail increased and leakage currents greatly reduced. The basic static CMOS gates such as inverter, NAND, NOR, and XOR circuits are designed based on SCLSB and their performance is evaluated using SPICE simulations in 22 nm CMOS BSIM4 process. Evaluation outcomes with VDD = 0.9 V depict that power-delay product (PDP) is diminished by 9%, 12.8%, 6%, and 15.25% for inverter, NAND, NOR, and XOR compared to the best counterpart (LECTOR) and by 9%, 35%, 21.5% and 33.8% compared to the conventional CMOS gates. The mentioned features of the proposed static-CMOS circuits are achieved while sustaining the full-swing behavior. To ensure the stability and robustness of the circuits in the presence of the process, voltage, and temperature (PVT) variations, Monte Carlo analysis is also performed.

Performance Comparison of the Conventional CMOS and MTCMOS Digital Circuits and Their Simulation

This paper focuses on the design of the conventional CMOS digital circuits and the Multi-Threshold CMOS (MTCMOS) digital circuits, which perform the specific Boolean logic function, as well as the comparison between these designing techniques by their functionality and power consummation (dissipation). The leakage of currents in integrated circuits based on CMOS logic becomes quite significant when the complementary MOS transistors are the small-device geometries (small dimensions), and this effect imposes alternative techniques that enable the designing of CMOS digital circuits with low-power dissipation, even in standby mode. One of these techniques is the design of the CMOS digital circuits with multi-threshold voltage (MTCMOS), which enables the reduction of the leakage power dissipation, as a part of the overall power dissipation in CMOS logic. Two CMOS digital circuits are designed (2-input XNOR CMOS gate and the other one is the CMOS gate that performs a complex Boolean function) based on conventional CMOS technique and multi-threshold voltage CMOS technique, and their functionality and calculation of the average overall power dissipation are tested using the Computer-Aided Design (CAD). The methodology used to achieve low power dissipation in CMOS digital circuits (MTCMOS) will be an efficient method for reducing the overall dissipation, while the high speed performance will be maintained.

A Thermally Stable Quasi-CMOS Bipolar Logic

Logic gates made of pairs of NPN and PNP bipolar transistors, similar to CMOS logic gates, have been proposed and patented long ago but did not find any practical application until now. Other bipolar technologies (TTL, TTL-S, ECL), once the technologies of choice for digital systems, were abandoned and superseded by CMOS. In this paper it is shown that now, when truly complementary pairs of bipolar transistors can be made, properly biased bipolar gates similar to CMOS gates are feasible, can be thermally stable and find practical applications.

Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models

Cryogenic CMOS is a crucial component in building scalable quantum computers, predominantly for interface and control circuitry. Further, high-performance computing can also benefit from cryogenic boosters. This necessitates an in-depth understanding of the power and performance trade-offs in the cryogenic operation of digital logic. In this article, we analyze digital standard cells in a 28 nm high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> metal gate (HKMG) CMOS foundry process design kit (PDK). We have developed Berkeley Short-channel IGFET Model (BSIM)4 of cryogenic CMOS and calibrated them with experimental measurements. Since low-temperature operation leads to an exponential decrease in the leakage current of the transistors, we further tune the threshold voltage of the devices to achieve iso-leakage. In this article, we present inverter static and dynamic characteristics and multiple ring oscillator (RO) structures. The simulation study shows that we can achieve 28% (FO4-RO) – 59% (NAND3-RO) higher performance under iso- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {DD}}$ </tex-math></inline-formula> scenario and up to 90% improvement in the energy-delay product (EDP) under iso-overdrive scenario at 6 K compared to room temperature.

Low-power 25Gb/s 16:1 Multiplexer for 400Gb/s Ethernet PHY

A lower power 25Gb/s 16:1 multiplexer using 65nm CMOS technology for 400Gb/s Ethernet (400GbE) physical layer (PHY) interface was presented. CMOS+CML mixed logic is adopted to achieve hierarchical architecture, avoiding the high clock requirement of one-step structure and improving the transmission speed. In order to reduce power while achieving high data rate, multiplexing structure is also optimized by utilizing multi-frequency multi-phase technology which not only ensures the requirement of the phase stabilization, but also leaves out some flip-flops. For CMOS-CML conversion circuit, transmission gate and cross-coupled CMOS inverter are used to match the delay of CMOS inverter, suppressing the effect of common-mode noise. Simulation results show that the multiplexer works correctly and jitter of output signal is less than 0.1UI. When voltage is 1.2V, the total power is 32.7mW at 25Gb/s.

Single-step reactive ion etching process for device integration of hafnium-zirconium-oxide (HZO)/titanium nitride (TiN) stacks

The integration of new materials such as high-k dielectrics or metals into advanced CMOS gate stacks has led to major developments in plasma etching. The authors present a study which is dedicated to the etching of amorphous hafnium zirconium oxide (HZO) and titanium nitride (TiN) layers with Ar/Cl2 chemistry in one single step. By adjusting the gas ratio and the inductively coupled plasma power, the etching process is shown to have a slow and well controllable etch rate for HZO and TiN. Additionally, a high selectivity between both materials and SiO2 can be achieved. Gate stack etching was successfully demonstrated and transmission electron microscopy-images revealed good anisotropic etching for HZO and TiN with an etch stop in SiO2 without damaging the silicon underneath. The process is further applied for the fabrication of metal-ferroelectric-metal capacitors, here TiN-HZO-TiN, and the feasibility of the chosen material combination is proven by electrical characterization. The strategy of using low temperature plasma-enhanced atomic layer deposition for TiN-deposition and forming gas anneal after structuring leads to high remanent polarization-values.

CryoMem: A 4–300-K 1.3-GHz Hybrid 2T-Gain-Cell-Based eDRAM Macro in 28-nm Logic Process for Cryogenic Applications

This letter demonstrates the first CMOS logic compatible cryogenic memory solution operating from 4 to 300 K designed in the 28-nm high-K metal gate (HKMG) CMOS. With the growing applications of cryogenic systems from quantum computing to space electronics, there is a need for memory capable of reliable functionality. While the prevailing low-temperature memories suffer from temperature scalability and integrability, the proposed test chip of 1-kb 2T hybrid gain cell-based embedded DRAM macro overcomes these issues while providing $10^{6} \times $ better retention time, 1.3-GHz peak frequency at 4 K, sub nW/kb array refresh power, and $1.7\times $ energy efficiency at 4 K compared to 300 K. This is due to the near absence of leakage, improved ON current, and subthreshold slope which leads to enhanced performance of critical path circuits at lower temperatures.

Design and Simulation of Reliable Low Power CMOS Logic Gates

In this paper, a circuit-level reliable low leakage design methodology is proposed for integrated circuits (ICs). Low leakage circuit design is the most challenging research area for very large-scale integration (VLSI) circuit designers due to the increased demand of battery-operated portable systems. Leakage power is increasing continuously with each new technology node generation in deep sub-micron (DSM) regime. Large power dissipation harms the device characteristics and affects the overall performance of the circuits. Proposed approach is extensively discussed and verified for the low power operation and reliability. The various logic circuits are simulated and compared with the available leakage minimization techniques at 22 nm technology node using predictive technology model (PTM) bulk CMOS BSIM4 on HSPICE tool. Proposed approach reduces leakage power by ≈81% in XOR2 and XNOR2 gates as compared to conventional CMOS gates. Reliability of the nanoscaled circuits is affected by several device parameters. Process, voltage and temperature (PVT) variations, aging and radiation effects are considered for reliability testing. The reliability of the proposed approach is improved by 77.45% for power delay product (PDP) metric for the ring oscillator as compared to conventional circuit.

Integration of Hafnium Oxide on Epitaxial SiGe for p-type Ferroelectric FET Application

Increasing demands for new computer architectures may require embedded non-volatile memories as for example in-memory computing. Ferroelectric field-effect transistors (FeFETs) add further advantages besides their outstanding properties due to the availability of both n-type and p-type transistors. The latter favor a different channel materials, like SiGe, due to the low hole mobility in silicon. In this article, we demonstrate the integration of ferroelectric hafnium oxide on SiGe as well as working p-type FeFETs, possessing a large memory window of about 1.1 V and low variability. Such architectures were co-integrated into a standard high-k metal gate (HKMG) CMOS platform. Furthermore, we report on the impact of annealing temperature on the interface and ferroelectric layer, which appears to be universal for SiGe and Si substrates. Here, a growth of the interface layer during annealing at higher temperatures was observed as well as a reduction of the wake-up effect for the ferroelectric layer.

QSTA: A Static Timing Analysis Tool for Superconducting Single-Flux-Quantum Circuits

Superconducting single-flux-quantum (SFQ) technology is a beyond-complementary metal–oxide–semiconductor (CMOS) technology, promising ultrahigh processing speed and low power consumption. A timing analysis tool for SFQ circuits should check circuit timing behavior, including working frequencies and hold time violations to determine the circuit performance. Unlike CMOS gates, generic SFQ gates are clocked gates, which produce their output pulses in response to a clock pulse and have a fan-out capability of one. An SFQ splitter, a special clockless gate that has a fan-out capability of two, is used to address the fan-out limitation. This gate is also utilized in the clock tree, which distributes clock pulses to various SFQ gates. The delay of a clock path in a clock tree is determined by the wire delays of connection nets and gate delays of splitters. However, the splitter delays in a clock path are significantly affected by process variations, resulting in a challenging skew problem. Furthermore, existing timing analysis tools of SFQ circuits are developed based on the timing definitions, rules, and constraints from CMOS technology with very few modifications. This article demonstrates the incompleteness of the existing SFQ technology timing definitions. Precisely, it presents a novel static timing analysis (STA) tool, qSTA, which checks the timing behavior of SFQ circuits based on revised definitions of the setup time and hold times. qSTA encompasses the common path pessimism removal technique, which removes the delays of the shared path segments between two clock paths to achieve a better approximation of real skew values. qSTA takes only 5.33 s to check the timing behavior of a 16-bit integer divider with 36 732 gates and 55 939 nets.

Computationally efficient compact model for ferroelectric field-effect transistors to simulate the online training of neural networks

In this paper, a compact drain current formulation that is simple and adequately computationally efficient for the simulation of neural network online training was developed for the ferroelectric memory transistor. Tri-gate ferroelectric field-effect transistors (FETs) with Hf0.5Zr0.5O2 gate insulators were fabricated with a gate-first high-k metal gate CMOS process. Ferroelectric switching was confirmed with double sweep and pulse programming and erasure measurements. Novel characterization scheme for drain current was proposed with minimal alteration of ferroelectric state in subthreshold for accurate threshold voltage measurements. The resultant threshold voltage exhibited highly linear and symmetric across multilevel states. The proposed compact formulation accurately captured the FET gate-bias dependence by considering the effects of series resistance, Coulomb scattering, and vertical field dependent mobility degradation.

(Invited) Development of CMOS-MEMS Cointegrated Pressure Sensor Using Minimal Fab Process

PVD-TiN metal gate PMOSFETs and CMOS ring oscillators have successfully been fabricated on circular diaphragms using the developed Minimal Fab CMOS-MEMS cointegrated gate-last process, and their electrical characteristics have systematically been investigated by changing applied pressures to the diaphragms. It was found that the drain current variation (dId) in the <110> channel PMOSFETs is larger than that in the <100> channel ones. The origin of dId is the mechanical stress-induced mobility change. It was also confirmed that the oscillation frequency of the fabricated CMOS ring oscillator on a circular diaphragm changes from 372 to 405 kHz at different pressures of -30 and +30 kPa. This result implies that the fabricated CMOS-MEMS cointegrated sensor chip is operated as a pressure sensor. The developed CMOS-MEMS cointegrated pressure sensor is suitable for the application to the battery drive IoT sensor systems because the all CMOS integration of the sensor has a low-power consumption.

CMOS low power split-drain MAGFET based magnetic field strength sensor

A low-power sectorial split-drain MAGFET (SSD-MAGFET) based magnetic field strength sensor consists of a simple counter-based time-to-digital converter was proposed, which converts the magnetic field strength into a digital value by observing the relative drain voltage difference in the SSD-MAGFET, thus eliminating the adverse effect of device and circuit noises without the need of sophisticated operational amplifier nor precise voltage reference. Complete digital readout of the magnetic field strength, field polarity and conversion time information facilitates the seamless integration of the proposed circuit to read-time application. The proposed circuit is fully compatible with standard CMOS process and the presented design example was implemented on 2.5 μm metal gate CMOS process which achieves conversion accuracy is of 1.226 mT/bit for the field range of a maximum dynamic range of ±313.96 mT, and the minimum conversion rate is 17.6 Hz where the whole chip consumes an average of 67.5 mW at supply voltage of 5 V, which is suitable for seamless integration with all sorts of MCU applications.

Subcircuit Pattern Recognition in Transistor Level Circuits

The paper presents a computer program for automatically extracting the hierarchy of a large-scale digital circuit from its transistor-level description derived from the layout of VLSI circuit. The considered problem arises in VLSI layout verification as well as in the circuit reengineering. The proposed subcircuit recognition algorithm extracts functional level structure from transistor-level circuit collecting transistors into gates without using any predefined cell library. The algorithm comes from a SPICE like network description and realizes three-step process. First, a structural approach in which gate structures are recognized as channel connected sequences of transistors is used. Then channel connected sequences of transistors which implement CMOS gates are searched for. And finally the method of subcircuit pattern recognition is used to gather the rest sequences of transistors into minimal number of classes of identical functional blocks. The presented algorithm has been implemented as a program in C++ and tested using practical transistor-level circuits.

Transmission Gate and Hybrid Cmos Full Adder Characterization and Power-Delay Product Estimation Based on Mathematical Model

Abstract The demand for low power CMOS VLSI circuit design is increasing due to the ever-increasing demand for portable devices. A Full Adder (FA) is the basic building block of many VLSI subsystems, and it affects the performance of VLSI subsystems. The Transmission Gate (TG) and hybrid CMOS FA designs can achieve low Power Delay Product (PDP) compared to other FA designs, hence these FA designs are suitable for portable devices. A large number of repetitive simulations are required for thorough characterization of the FA design. A method to develop the mathematical model (based on 2nd degree polynomial equation) of the FA is proposed here, which satisfactorily estimates the Power Delay Product (PDP) of TG and hybrid CMOS FAs for non-simulated parameter combinations within given parameter range. Main aim of proposed method is to reduce characterization effort by estimating PDP using mathematical model, rather than estimating it through simulation. Also, mathematical model can be used to estimate the transistor widths to achieve low PDP for particular operating condition. Further, the effect of individual polynomial term, number of parameters, and number of points per parameter, on the accuracy of mathematical model is also studied.

A 24-MB Embedded Flash System Based on 28-nm SG-MONOS Featuring 240-MHz Read Operations and Robust Over-the-Air Software Update for Automotive Applications

This letter presents an embedded flash (eFlash) system based on 28-nm split-gate MONOS (SG-MONOS) with high- ${k}$ metal gate CMOS process technology for automotive applications. It contains the world’s largest 24-MB memory capacity (4-MB code flash macro (CF) $\times6$ ) and achieves 240-MHz random read access at Tj from −40 °C to 170 °C, and read throughput reaches 46 GB/s by reading 6 CFs in parallel. The peak current consumption during over-the-air software update (OTA) is reduced by 55% in low-noise program mode. A high-speed program mode for factory program and test achieves 6.5-MB/s program throughput by programming 2 CFs in parallel. In OTA, the eFlash system realizes ~1 ms software switching and robustness against unintentional OTA termination.

In-situ heater for thermal assist recovery of MOS devices in 28 nm UTBB FD-SOI CMOS technology

Preliminary results are reported on an in-situ heater for thermal assist recovery of MOS transistor and is demonstrated in 28 nm Fully Depleted Silicon-On-Insulator (FD-SOI) Ultra-Thin Body and Buried oxide (UTBB) high-k metal gate CMOS technology. This approach consists in functionalizing the source of a MOS device. We demonstrate that it is possible to heat the device with the current flowing between two split source contacts. Electrical and temperature measurements of the structures were made at wafer level. Moreover, 3D TCAD electro-thermal simulations assess the concept. The thermal resistor calibration on source and gate are performed on low and high VT NMOS devices with thin and thick high-k metal gate oxide. We have successfully reproduced the I-V responses on several samples at wafer level by electrical sweep in the 100 ns range into the split source contacts. The local temperature change effect was measured from room temperature up to +300 K. Finally, this first study shows that the thermal recovery is efficient and opens the door on new innovative solutions and could be applied on other technology nodes.

A QUAD CMOS GATES CHECKING METHOD

The so-called Fault-Tolerant Systems (FTS) use the structural, temporal, functional, or information redundancy for the achievement of the high reliability. For example, Radiation Hardened by Design (RHBD) Systems are Fault-Tolerant Systems. A Passive FTS, due to a very large structural redundancy (Modular Redundancy), produces faults masking. The Triple Modular Redundancy (TMR) Method has more than 300% redundancy. The Quad Redundancy (QR) Method boasts more than 400% redundancy. The CMOS transistors QR (transistor-level redundancy) is the most effective QR. In this case, no voting element is needed. However, this significantly increases the time delay. In addition, it is necessary to ensure compliance with the Mead-Conway restrictions. QR, in contrast to TMR, raises the problem of checking the redundant structure. The author proposes a QR Checking Method based on a selection of substrates of the CMOS transistors. The power lines of the transistor substrates are separated, which ensures the disconnection of part of the reserve. A simulation confirms the feasibility of the proposed method.

Improving the performance of transmission gate and hybrid CMOS Full Adders in chain and tree structure architectures

A Full Adder (FA) is the basic building block of many VLSI sub-systems, and generally it falls into the critical path of the system. Several Transmission Gate (TG) and hybrid CMOS FA designs have been proposed in literature to achieve low Power Delay Product (PDP). But, their performance degrades when used in chain and tree structures, mainly due to poor driving capability. This paper introduces new design approach, a triplet design, to improve performance of TG and hybrid CMOS FA designs in chain and tree structures without inserting buffers. Two new hybrid CMOS FA designs, which are suitable for triplet design approach are also proposed in this paper. Six different FA designs (TG and hybrid CMOS FAs) are chosen to build 4, 8 and 16 bit Ripple Carry Adders (RCA) and multipliers, and we also studied the improvement in PDP using triplet design approach. Schematics and layouts of RCA and multiplier are designed in Cadence Virtuoso using gpdk045 library, and compared based on PDP.