CryoMem: A 4–300-K 1.3-GHz Hybrid 2T-Gain-Cell-Based eDRAM Macro in 28-nm Logic Process for Cryogenic Applications

Abstract

This letter demonstrates the first CMOS logic compatible cryogenic memory solution operating from 4 to 300 K designed in the 28-nm high-K metal gate (HKMG) CMOS. With the growing applications of cryogenic systems from quantum computing to space electronics, there is a need for memory capable of reliable functionality. While the prevailing low-temperature memories suffer from temperature scalability and integrability, the proposed test chip of 1-kb 2T hybrid gain cell-based embedded DRAM macro overcomes these issues while providing $10^{6} \times $ better retention time, 1.3-GHz peak frequency at 4 K, sub nW/kb array refresh power, and $1.7\times $ energy efficiency at 4 K compared to 300 K. This is due to the near absence of leakage, improved ON current, and subthreshold slope which leads to enhanced performance of critical path circuits at lower temperatures.