Subcircuit Pattern Recognition in Transistor Level Circuits

Abstract

The paper presents a computer program for automatically extracting the hierarchy of a large-scale digital circuit from its transistor-level description derived from the layout of VLSI circuit. The considered problem arises in VLSI layout verification as well as in the circuit reengineering. The proposed subcircuit recognition algorithm extracts functional level structure from transistor-level circuit collecting transistors into gates without using any predefined cell library. The algorithm comes from a SPICE like network description and realizes three-step process. First, a structural approach in which gate structures are recognized as channel connected sequences of transistors is used. Then channel connected sequences of transistors which implement CMOS gates are searched for. And finally the method of subcircuit pattern recognition is used to gather the rest sequences of transistors into minimal number of classes of identical functional blocks. The presented algorithm has been implemented as a program in C++ and tested using practical transistor-level circuits.