CMOS Flash Research Articles

A Brief History of Nyquist Analog-to-Digital Converters

This paper reviews and discusses a brief history of Nyquist ADCs. Bipolar flash ADCs for early development stage of HDTV and digital oscilloscopes, a Bi-CMOS two-step flash ADC using resistive interpolation for home HDTV receivers, a CMOS two-step flash ADC using capacitive interpolation for handy camcorders, pipelined ADCs using CMOS operational amplifiers, CMOS flash ADCs using dynamic comparator and digital offset compensation, SAR ADCs using low noise dynamic comparators and MOM capacitors, and hybrid ADCs are reviewed.

Low Area and High Bit Resolution Flash Analog to Digital Converter for Wide Band Applications: A Review

: This work reviews the design challenges of CMOS flash type Analog-to-Digital Converter (ADC) for making high bit resolution, low area, low noise, low offset, and power-efficient architecture. Low-bit resolution flash ADC architecture, high-speed applications, and wide-area parallel comparators are identified on their suitability of the design for ADCs. These are effective in the area and bit resolution. The overview includes bit resolution, area, power dissipation, bandwidth and offset noise consideration for high-speed flash ADC design. A MUX-based two-step half flash architecture is considered for applications requiring 1 GHz 16-bit resolution low area and low power consumption. An advanced comparator, MUX, a high-speed digital-to-analog converter (DAC), and MUX-based encoder are also reviewed. The design of technology-efficient ADC architecture is highly challenging for the analog designer.

Graphene Photo Memtransistor Based on CMOS Flash Memory Technology with Neuromorphic Applications

Graphene holds a great promise for a number of diverse future applications, in particular related to its easily tunable doping and Fermi level by electrostatic gating. However, as of today, most implementations rely on electrical doping via the application of continuous large voltages to maintain the desired doping. We show here how graphene can be implemented with conventional semiconductor flash memory technology in order to make programmable doping possible, simply by the application of short gate pulses. We also demonstrate how this approach can be used for a memory device, and also show potential neuromorphic capabilities of the device. Finally, we show that the overall performance can be significantly enhanced by illuminating the device with UV radiation. Our approach may pave the way for integrating graphene in CMOS technology memory applications, and our device design could also be suitable for large scale neuromorphic computing structures.

A flashback for resistive memory

Purely electronic memristive devices based on CMOS flash memory technology could lead to large-scale neuromorphic systems.

Design of Efficient Low Power Flash ADC Using TIQ in 45 nm Technology

Objective: To design and implement flash ADC for high speed operation thereby to minimise the power consumption and improve the performance efficiency. Methods: At present, there exists a variety of Analog-to-Digital Converter (ADC) with different architecture, sampling rates, resolutions, temperature ranges, and power consumption. The existing ADCs used in various multiple applications which include mobile communication hardware to measuring instruments. Therefore, their significant performance and working of ADCs are determined by its architecture, the commonly existing ADC design is not suitable for all applications. In order to meet the high speed operation scenario, a Flash type ADC model is proposed. Findings: Resistor ladder would be commonly used in all type of ADC circuits, but downside it consume maximum area and power. In all existing methods, the average power consumption of Flash ADC is found to be higher when compared with our methodology. This can be overcome by using threshold inverting quantization (TIQ) comparator for low power operation. Improvements: An efficient thermometer to the binary code converter is targeted for 45 nm CMOS technology that has been proposed and implemented Flash CMOS ADC Design using the CADENCE VIRTUOSO Tool. The optimal power analysis has been carried out to prove the design absolutely a low power model.Keywords: Flash ADC, Low Power, CMOS Technology, TIQ Comparator, CADENCE VIRTUOSO

TIQ Flash ADC Design using a Low Power Multiplier Based Encoder

Threshold Inverter Quantization (TIQ) for applications of system-on-chip (SoC) depending on CMOS flash analog-to-digital converter (ADC). The TIQ technique which uses two cascaded CMOS inverters as a voltage comparator. However, this TIQ method must be created to meet the latest SoC trends, which force ADCs to be integrated with another electronic circuit on the chip and focus on low-power and low-voltage applications. TIQ comparator reduced the impact of variations in the process, temperature, and power supply voltage. Therefore, we obtained a higher TIQ flash ADC speed and resolution. TIQ flash ADC reduced / managed power dissipation. We obtain large power savings by managing the power dissipation in the comparator. Furthermore, the new comparator has a huge benefit in power dissipation and noise rejection comparative to the TIQ comparator [1]. The findings indicate that the TIQ flash ADC based on Modied mux attain heavy-speed transformation and has a tiny size, low-power dissipation and operation of lowvoltage compared to another flash ADCs.

Review of Millimeter-Wave Integrated Circuits With Low Power Consumption for High Speed Wireless Communications

Abstract In this paper we review high-speed radio-frequency integrated circuits operating up to 210 GHz and present selected state-of-the-art circuits with leading-edge performance, which we have designed at our chair. The following components are discussed employing bipolar complementary metal oxide semiconductors (BiCMOS) technologies: a 200 GHz amplifier with 17 dB gain and around 9 dB noise figure consuming only 18 mW, a 200 GHz down mixer with 5.5 dB conversion gain and 40 mW power consumption, a 190 GHz receiver with 47 dB conversion gain and 11 dB noise figure and a 60 GHz power amplifier with 24.5 dBm output power and 12.9 % power added efficiency (PAE). Moreover, we report on a single-core flash CMOS analogue-to-digital converter (ADC) with 3 bit resolution and a speed of 24 GS/s. Finally, we discuss a 60 GHz on-off keying (OOK) BiCMOS transceiver chip set. The wireless transmission of data with 5 Gb/s at 42 cm distance between transmitter and receiver was verified by experiments. The complete transceiver consumes 396 mW.

Design of a Touch Controller for Multi-Touch Screen System with Touch Prediction and Window Sensing (TPWS) Strategy

The touch prediction and window sensing (TPWS) strategy is an effective approach to realize low-cost and low-power multitouch screen systems, especially for large-sized touch screen panels. The structures of traditional touch controller using charge integrating amplifier is not suitable for the TPWS touch screen systems. This paper presents a new touch controller, which is designed for the TPWS touch screen systems and is emphasized to improve the SNR and reporting rate of system. The differential measurement scheme with a full driving method is proposed to eliminate the influences on the SNR and the reporting rate of system caused by the LCD noise, the charger noise and the signal transmission delay on Indium-Tin Oxide (ITO) electrodes. The designed touch controller is realized in a 0.13 µm 1.8 V/5 V embedded flash CMOS process with the chip size of 2.5 × 2.8 mm2. The test results demonstrate that this touch controller supports the TPWS strategy very well and its performances are improved significantly. Comparing with the previous design, the SNR is improved from 25 to 36 dB, and the reporting rate is increased from 83 to 120 Hz.

Identification of current transport mechanism in Al2O3 thin films for memory applications

The effect of oxygen anneal on the electrical characteristics, especially on the current transport mechanism, of Al2O3 films in the thickness range of 10–30 nm was examined in detail. The analyses were performed at electric fields of ≤2.5 MV/cm to effectively address the reliability of Al2O3-based devices operating in the low electric field regime. The general conduction mechanism equations were used to simulate the expected current density (J) values for a given electric field (E) range. The characteristic linear plots of the conduction mechanisms were then used to compare the experimental and simulated data to identify the most probable mechanism occurring in the dielectric. Parameters like barrier height and activation energy were extracted from the fit. It was found that oxygen anneal has profound effects on the electrical properties of Al2O3 films, with annealed films demonstrating a different conduction mechanism than their unannealed counterparts, along with significant improvement in the leakage current and barrier height. This kind of analyses will help optimize the process conditions for Al2O3 deposition and provide an optimal range for device operation, thus improving the reliability of Al2O3 films for applications in CMOS logic and Flash memory.

A novel autozeroing technique for flash Analog-to-Digital converters

This paper presents a new autozeroing technique that combines very high speed operation, low power consumption and low input switching interferences. This technique has been applied to the design and implementation of a 6-bit 0.13μm CMOS flash Analog-to-Digital converter for Ultra-Wide Band applications. Simulation results show 5.76-bit at 1GS/s with a power consumption of only 182mW, validated with experimental measurements carried out with 3-bit circuit tiles of the 6-bit flash A/D converter.

A BISECTION-BASED POWER REDUCTION DESIGN FOR CMOS FLASH ANALOG-TO-DIGITAL CONVERTERS

In this paper, we present a bisection-based power reduction design for CMOS flash analog-to-digital converters (ADCs). A comparator-based inverter is employed along with two switches of an NMOS and a PMOS, the bisection method can let only half of comparators in a flash ADC work in every clock cycle for reducing power consumption. A practical example of 6-bit flash ADC operates at 200 MHz sampling rate and 3.3 V supply voltage is demonstrated. The power consumption of proposed circuit is only 40.75 mW with HSPICE simulation. Compared with the traditional flash ADC, our bisection method can reduce up to 43.18% in terms of power dissipation.

An efficient power reduction technique for CMOS flash analog-to-digital converters

An efficient power reduction technique for CMOS flash analog-to-digital converter (ADC) is presented. The presented technique adopts the procedure with a simple coarse comparison first followed by a finer comparison later. Our ADC design does not decrease the total number of comparators, though it is able to reduce the power consumption. Subject to time signal controlling, the manipulation is to interchangeably shut down the comparator sections for the coarse comparison function. Experimental results show that this new method consumes about 48.14 mW at 400 MHz with 3.3 V supply voltage in TSMC 0.35 μm 2P4 M process. Compared with the traditional flash ADC, our low power method can reduce up to 47.8% in power consumption. The DNL of our proposed flash ADC is 0.5 LSB, the INL is 0.7 LSB, and the ENOB is 5.75 bits. The chip area occupies 0.4 × 0.9 mm2 without I/O pads.

Flash analog-to-digital converter operational in an ultra wide temperature range (room temperature to 4.2 K) in standard CMOS technology using a cryogenic reset switching scheme

This work presents the design and test result of a standard 0.7 μm CMOS flash analog-to-digital converter (ADC) operational in an ultra wide temperature range (UWT, room temperature down to 4.2 K). To maintain the circuit’s performance over the UWT range in the presence of temperature induced transistor anomalies, dedicated topology and switching schemes are utilized. Test results mentioned in this text are from a single process run, no design iterations were made.

A 1.2 V 7-bit 1 GS/s CMOS Flash ADC with Cascaded Voting and Offset Calibration

A 1.2 V 7-bit 1 GS/s CMOS flash ADC with an interpolation factor of 4 is implemented by using a 0.13 ㎛ CMOS process. A digital calibration of DC reference voltage is proposed for the 1<SUP>st</SUP> preamp array to compensate for the input offset voltage of differrential amplifiers without disturbing the high-speed signal path. A 3-stage cascaded voting process is used in the digital encoder block to eliminate the conescutive bubbles up to seven completely, if the 2<SUP>nd</SUP> preamp output is assumed to have a single bubble at most. ENOB and the power consumption were measured to be 5.88 bits and 212 ㎽ with a 195 ㎒ 400 ㎷<SUB>p-p</SUB> sine wave input.

FN Stress Induced Degradation on Random Telegraph Signal Noise in Deep Submicron NMOSFETs

As the gate area decreases to the order of a square micron, individual trapping events can be detected as fluctuations between discrete levels of the drain current, known as random telegraph signal (RTS) noise. Many circuit application areas such as CMOS Image sensor and flash memory are already suffering from RTS noise. Especially, in case of flash memory, FN stress causes threshold voltage shift problems due to generation of additional oxide traps, which degrades circuit performance. In this paper, we investigated how FN stress effects on RTS noise behavior in MOSFET and monitored it in both the time domain and frequency domain.

Cascaded voting process for flash ADC with interpolating scheme

A 3-stage cascaded voting process is proposed for flash analogue-to-digital converters (ADCs) with an interpolation factor of 4 to eliminate the consecutive bubbles at the output nodes of the comparator array. Compared to the conventional 3-input voting process, the proposed process completely eliminates up to seven consecutive bubbles without hardware overhead, if the preamplifier output is assumed to have a single bubble at most. The proposed voting process is evaluated by 7-bit 1 GS/s CMOS flash ADCs with an interpolation factor of 4 which is designed by a 0.13 m CMOS process with 1.2 V supply.

A 1.3-Gsample/s interpolation with flash CMOS ADC based on active interpolation technique

In this paper, the design of a high-speed low-voltage CMOS interpolation with flash analog-to-digital converter (ADC) in CMOS 0.18-?m process is presented. The use of summing differential amplifiers operating in continuous time for interpolation and resistor averaging circuit have significantly improved the circuit's linearity. The new interpolation technique has improved the pertinent phase delay problem of voltage interpolation enormously. A technique to reduce metastability errors in the Error Correction Circuitry is also presented. The circuit achieves a maximum sampling speed of 1.3 GHz. The measured signal-to-noise-plus-distortion ration (SNDR) is 32 dB at 500 MHz. Peak DNL and INL are less than 0.15 LSB and 0.35 LSB, respectively. This ADC consumes about 600 mW from 1.8 V at full speed. The chip occupies 0.56-mm2 active area, prototyped in CMOS 0.18-?m technology.

A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS

The design and optimization of a high-speed low-voltage CMOS flash analog-to-digital converter (ADC) are presented. The optimization procedures used during the design give the needed specifications of the different building blocks. Also, an extensive description of the implemented digital error correction technique is described. The used analog power supply is only 1.8 V. The maximum sampling speed is 1.3 GHz. The signal-to-noise-plus-distortion ratio (SNDR) at 133 kHz is 33.2 dB, and the SNDR at 500 MHz is 32 dB. The total power consumption of the converter at full speed is 600 mW and the total active area is only 0.13 mm/sup 2/. The ADC is implemented in a 0.25-/spl mu/m pure digital CMOS technology.

6-bit 500 MHz flash A∕D converter with new design techniques

The authors present a 6-bit 500 Msample/s CMOS flash analogue-to-digital converter (ADC) with new design techniques. A technique referred to as the new autozeroing with interpolation (NAI) technique is proposed to include both autozeroing without idle time and interpolation operations at the same time in this high-speed low-latency flash ADC. A switching preamplifier is used in NAI to avoid using non-overlapped control signals required by conventional autozeroing ADCs and to eliminate the interference, caused by the high-speed autozeroing operation, at input nodes. Also, NAI has the benefit of a single-phase control to avoid synchronisation problems since multiphase clock signals are necessary for flash ADCs with autozeroing. While charge injection and feedthrough in NAI limit the ADC performance, a capacitor averaging technique is incorporated with NAI to decrease these errors. A negative impedance compensation technique is used to overcome the speed limitation of interpolation operations so that the ADC can operate at a high sampling rate. The designed ADC is fabricated in 0.25 μm 1P5M CMOS technology and occupies an active area of 0.3 mm2. The measurement results show that the design can achieve a sampling rate of 500 MHz with a SNR&gt;30 dB. The total chip draws 261 mW from a 2.5 V power supply.

Comparator Generation and Selection for Highly Linear CMOS Flash Analog-to-Digital Converter

This paper presents a comparator generation and selection method to reduce the linearity errors—DNL and INL—for a CMOS flash analog-to-digital converter (ADC) based on threshold inverter quantization (TIQ) technique. The TIQ flash ADC requires 2n − 1 comparators like conventional flash ADCs. However, each comparator in the TIQ flash ADC has different sizes to provide internal reference voltages, while the differential comparators have identical sizes. The design method has been incorporated into a software package and the 2n − 1 optimized TIQ comparator layouts are generated as an output of the software package. The linearity errors against the CMOS process, power supply voltage, and temperature variations are significantly improved by the proposed comparator generation and selection method for the TIQ flash ADC. Especially, the DNL dependence on the CMOS process variation can be almost eliminated. The simulation results show 82.6% of DNL and 32.5% of INL improvements against CMOS process variation. For the other variations—power supply voltage and temperature—43.5% for DNL and 6.0% for INL improvement has been achieved. The prototype chips have been fabricated and the chip test results confirms the simulation results.