CMOS Flash Research Articles

A single-chip text-to-speech synthesis device utilizing analog nonvolatile multilevel flash storage

A single-chip solution for text-to-speech synthesis is presented. The chip utilizes analog nonvolatile multilevel storage (MLS) to store a corpus of natural speech elements. Synthesis is achieved by concatenating speech elements together at the word, subword, syllable, or phoneme level. An embedded micro-controller with custom peripherals performs the algorithmic tasks of the text-to-speech synthesis, namely text normalization, phonetic translation, and corpus phoneme selection. The chip is controlled via an SPI serial bus and synthesized speech is available as both analog and digital PCM audio. The chip has been fabricated in 0.5-μm flash CMOS.

A 44-mm/sup 2/ four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller

The highest bit-density 64-Mb NOR flash memory with dual-operation function of 44 mm/sup 2/ was developed by introducing negative-gate channel-erase NOR flash memory cell technology, 0.16-/spl mu/m CMOS flash memory process technology, and four-bank hierarchical word-line and bit-line architecture. The chip has flexible block redundancy for high yield, a fast accurate word-line voltage controller for a fast erasing time of 0.5 s, and an eight-word page-read access capability for high read performance of an effective access time of 30 ns at a wide supply voltage range of 2.3-3.6 V.

Influence of the polysilicon doping on the electrical quality of thin oxides: a confrontation between vertical and horizontal furnaces

In this work, the influence of polysilicon doping on thin oxides (thickness equal or below 10nm) quality and reliability (thickness equal or below 10nm) in MOS capacitors with polysilicon gate is evaluated. By observing the polysilicon deposed in vertical and horizontal furnaces, a higher degradation in the oxide–silicon interface at high doping concentration has been found. In the case of vertical furnaces, a more evident charge trapping in the constant current stress (CCS) V(t) curves and Qbd (ERCS) degradation have also been noticed. Resistivity measurements at different concentrations show a saturation effect just in correspondence of the oxide degradation. From a morphological point of view, the poly deposited in vertical furnaces consists of grains which are larger than the ones found in horizontal furnace polysilicon and contains lower microdefectivity. Starting from these observations a model explaining the polysilicon morphology role in the oxide reliability can be proposed. According to it, the degradation of the interface is caused by the phosphorus coming from the “in situ” doped polysilicon. The hypothesis is that, at high concentrations and in presence of very large polysilicon grains, phosphorous cannot segregate at the interfaces among the polysilicon grains and, moving through the thin oxide, damages the silicon interface. This model has been confirmed by electrical, AFM and TEM analysis and all the collected data have been related to the finished devices performances (yield and reliability of CMOS flash memories, 0.25μm technology and below).

Behavioral model of a 1.8 V 6B CMOS flash ADC based on device parameters

A hierarchical behavioral model of a submicron 6 bit CMOS flash analog to digital converter is presented. Circuit parameters are extracted from process dependent device data using an extension of the g/sub m//I/sub D/ methodology for use in the behavioral model. In using this approach, the model will track changes in physical device geometries without the need for re-characterization. The comparator model is validated against SPICE and system level simulation results are presented for the full converter.

Limitation of the TiN/Ti layer formed by the rapid thermal heat treatment of pure Ti films in an NH/sub 3/ ambient in fabrication of submicrometer CMOS flash EPROM IC's

In this study, the technical feasibility and limitation of the TiN film formed by the rapid thermal heat treatment (RTHT) in an ammonia ambient for the fabrication of 0.85-/spl mu/m CMOS flash electrically programmable read only memory (EPROM) integrated circuits having a contact aspect ratio of approximately 1.5, were investigated. When the as-deposited thickness of the Ti film was less than 130 /spl Aring/, all memory contacts exhibited an "electrically open" contact signature (>4750 /spl Omega//contact). Transmission electron microscopy (TEM) cross section examination of a failed contact chain structure indicated that the failure mechanism could be a physical separation at the W-plug/silicon interface. For the Ti films with thickness between 130 and 240 /spl Aring/, the contact resistance dropped to a value between 59 and 68 /spl Omega//contact. Furthermore, the contact failure rate (contacts exhibiting "electrically open" signature) decreased as the thickness of the Ti film increased. In this case, the failure mechanism appeared to be the direct contact between the TiN layer and the silicon at the contact interface. This condition was created during the multistep nitridation process where approximately 240 to 250 /spl Aring/ of the Ti film was converted to TiN. For the memory devices having Ti films thicker than 240 /spl Aring/, all memory contacts were electrically and mechanically stable, and exhibited equivalent or higher circuit yields compared to devices having a sputter deposited TiN/Ti bilayer film (control group).

A CMOS 6-b, 200 MSample/s, 3 V-supply A/D converter for a PRML read channel LSI

A CMOS 6-b, 200 MSample/s, (MS/s) flash A/D converter (ADC) with 3 V power supply has been developed for a mixed-signal partial-response maximum likelihood (PRML) read channel LSI. In a CMOS flash ADC with chopper comparators, all comparators are auto-zeroed prior to each conversion. As a result, half of the available comparison time is spent autozeroing. To improve conversion rate and performance when included in a mixed-signal LSI, the auto-zeroing rate was reduced using a newly developed "interleaved auto-zeroing" (IAZ) architecture. Less frequent auto-zeroing also reduces kickback noise to the analog input and reference resistor string and power supply noise. In addition, the comparator output-swing is limited to improve recovery from large overdrives by adding diode connected transistors. This "output-swing limiting comparator" (OLC) improved the response to high frequency analog inputs. A conversion rate of 200 MS/s was achieved in the PRML read channel LSI using the IAZ architecture and OLC. This ADC was fabricated with single poly-Si, double-Metal, 0.5-/spl mu/m CMOS technology.

Manufacturing issues related to RTP induced overlay errors in a global alignment stepper technology

The effect of rapid thermal processing on wafer distortion and overlay accuracy in global alignment photolithography in the fabrication of 0.85 /spl mu/m CMOS Flash EPROM integrated circuits was studied. Both rapid thermal process parameters and system design (single and multi-lamp processors) were evaluated for their effect on overlay accuracy. It was found that a rapid thermal process (following contact etch and ion implantation) at set temperatures greater than or equal to 950/spl deg/C resulted in interconnect metallization-to-contact overlay errors in excess of 1.0 /spl mu/m across the wafer, which led to a 20% functional circuit yield loss. In the case of the single lamp processor, this misalignment was attributed to wafer distortion due to the temperature overshoot during the ramp step, which subsequently resulted in an across wafer temperature range of greater than 120/spl deg/C. This temperature overshoot and nonuniformity was eliminated by reducing the ramp rate below 100/spl deg/C/s. This ramp rate reduction, however, decreased the system wafer throughput, and required optimization to eliminate the overlay errors and minimize the effect on throughput. In this study, a 60/spl deg/C/s ramp rate was found to be optimum. For the multi-lamp RTP system, the metal-to-contact overlay error was not observed. This was believed to be due to the design of the heating mechanism in the multi-lamp processor, which did not produce the large wafer temperature overshoot and nonuniformity that was observed in the single lamp processor.

A 5-V-only 16-Mb flash memory with sector erase mode

A 5-V-only 16-Mb CMOS flash memory with sector erase mode is described. An optimized memory cell with diffusion self-aligned drain structure and channel erase are keys to achieving 5-V-only operation. By adopting this erase method and row decoders to apply negative bias, 512-word sector erase can be realized. The auto chip erase time of 4 s has been achieved by adopting 64-b simultaneous operation and improved erase sequence. The cell size is 1.7 mu m*2.0 mu m and the chip size is 6.3 mm*18.5 mm using 0.6- mu m double-layer metal triple-well CMOS technology. >

Analysis of reference‐tap‐voltage fluctuation in flash A/D converter

AbstractTo improve the speed and accuracy of the CMOS flash A/D converter using a copper‐type comparator, an analysis has been performed for the voltage variation at each reference terminal of the ladder resistor providing a reference voltage. A model has been developed in which the circuit made of the ladder resistor and the input capacitance of the comparator is treated as a distributed network. A theoretical formula is derived which analytically provides transient behavior of each reference terminal voltage due to change in the comparator. With this formula, it is found that the maximum error of the reference terminal voltage occurs when the input voltage is either 0 or V ref. The error decreases exponentially with reduction of ladder resistors and comparator input capacitances and with increase of time. It is found that the product of the ladder resistor and the comparator input capacitance between adjacent terminals must be less than 5 × 10−13 F.Ω in order to obtain an 8 bit A/D converter with 20 MS/s. Variation is decreased if the midpoint of the ladder resistor is fixed. For instance, when the midpoint is fixed, the product of the ladder resistor and the comparator input capacitance is allowed to increase up to 2 × 10−12 F.Ω.