Abstract
A 1.2 V 7-bit 1 GS/s CMOS flash ADC with an interpolation factor of 4 is implemented by using a 0.13 ㎛ CMOS process. A digital calibration of DC reference voltage is proposed for the 1<SUP>st</SUP> preamp array to compensate for the input offset voltage of differrential amplifiers without disturbing the high-speed signal path. A 3-stage cascaded voting process is used in the digital encoder block to eliminate the conescutive bubbles up to seven completely, if the 2<SUP>nd</SUP> preamp output is assumed to have a single bubble at most. ENOB and the power consumption were measured to be 5.88 bits and 212 ㎽ with a 195 ㎒ 400 ㎷<SUB>p-p</SUB> sine wave input.
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