A real-time pseudo-background gain calibration strategy for residue amplifiers of pipeline ADCs

Abstract

A pseudo-background continuous-time strategy is developed for gain and offset calibration in open-loop inter-stage residue amplifiers of pipeline ADCs. The ping-pong calibration strategy is enhanced for loop gain and accuracy to be utilized for open-loop RAs. Thanks to a reliable technique for preserving analog voltages for long time durations, data conversion continuously proceeds. In addition, other advantages of the foreground techniques, like lower power consumption and smaller area are achieved. The reduction in power consumption due to the elimination of a wide-bit digital processor easily overcomes the increase which stems from the replica residue amplifier. Storing the calibration results in reliable analog storages, the multiplexing frequency and clock frequency within the calibration loop are reduced to 100 KHz, respectively, which result in a significant amount of power reduction. Monte-Carlo analysis for 100 iterations shows that the calibration loop provides an absolute gain of 4 with the median value of 3.996 and standard deviation of 0.003, while the threshold voltages and reference levels experience a Gaussian distribution with 25 mV variations at 3σ. Total power consumption equals 1.8 mW for both the offset and gain calibration at 1.8 V (and 3.3 V for DAC) supply voltage. More than 9-bit accuracy is obtained at 50 mV peak-to-peak residue. Linearity is reduced to 7-bits for full-swing input range. Also, 13 dB and 8 dB improvement in SNDR and SFDR of a 13-bit 100S/s pipeline ADC is achieved when the offset and gain calibration loops are activated. Post-Layout simulation results are presented at all process corners using the BSIM3v3 model of a 0.18 μm CMOS technology.