A 1.3-Gsample/s interpolation with flash CMOS ADC based on active interpolation technique

Abstract

In this paper, the design of a high-speed low-voltage CMOS interpolation with flash analog-to-digital converter (ADC) in CMOS 0.18-?m process is presented. The use of summing differential amplifiers operating in continuous time for interpolation and resistor averaging circuit have significantly improved the circuit's linearity. The new interpolation technique has improved the pertinent phase delay problem of voltage interpolation enormously. A technique to reduce metastability errors in the Error Correction Circuitry is also presented. The circuit achieves a maximum sampling speed of 1.3 GHz. The measured signal-to-noise-plus-distortion ration (SNDR) is 32 dB at 500 MHz. Peak DNL and INL are less than 0.15 LSB and 0.35 LSB, respectively. This ADC consumes about 600 mW from 1.8 V at full speed. The chip occupies 0.56-mm2 active area, prototyped in CMOS 0.18-?m technology.