Digitally Calibrated 768-kS/s 10-b Minimum-Size SAR ADC Array With Dithering

Abstract

Array sensors require a high-performance analog-to-digital converter (ADC) array with small area and low power. Successive-approximation register (SAR) ADC has good potential for ADC array due to its simple analog circuits. However, SAR ADCs with 10-b resolution and higher normally need a large capacitor array due to the stringent matching requirement. The large capacitor array also limits the ADC dynamic performance. The capacitor mismatch has been compensated by analog calibration techniques. In this work, a novel digital calibration method is developed for SAR ADC based on dithering. With dithering, weights of most significant bit (MSB) capacitors can be measured accurately so that very small capacitors can be used in the SAR ADC due to the relaxed matching requirement. A modified bit-cycling procedure is developed to avoid the code gaps caused by capacitor dithering. This calibration technique requires no analog calibration overhead and simple digital decoders. The technique is implemented in an ADC array design including 256 SAR ADCs for a high-speed CMOS imaging sensor in a 0.18-μm CMOS process. The 10-b SAR ADC is designed with the minimum capacitor array size in the process. A single SAR ADC only occupies 15 μm × 710 μm. Sampling at 768 kS/s, peak DNL and peak INL of the original ADCs averaged across the array are 0.82 least significant bit (LSB) and 3.85 LSB, respectively. For a signal close to the Nyquist frequency, original ADCs have 7.96-b average ENOB. After calibration with dithering, ADCs have 0.55-LSB peak DNL and 0.77-LSB peak INL averaged across the array. The average ENOB improves to 9.83 b. Compared with the benchmark 10-b SAR ADCs, this design is the most area-efficient design. In this work, the calibration decoders are implemented off-chip. With a sample-and-hold amplifier, the calibration method can run in the background.