Abstract
This study presents a new method for the design of a N-bit successive approximation register (SAR) analog-to-digital converter (ADC) which employs the main-scale Vernier-scale characteristics of a Vernier caliper. The proposed design is similar to a half-SAR design where the main half-SAR ADCs the N/2 most significant bits (MSBs) from comparisons of the input signal with all of the quantization thresholds, while the Vernier (scale) half-SAR ADCs the N/2 least significant bits (LSBs). Relative to previous designs, this architecture reduces the number of comparators while maintaining high resolution and speed. A 12-bit prototype is tested by code density analysis, showing Integral Nonlinearity (INL) within ±1.0 LSB and Differential Nonlinearity (DNL) within ±0.5 LSB. Resolution is strongly dependent on precision current sources and resistor ladders. Such requirements, however, are easily met with very-large-scale integrated (VLSI) technologies, making the Vernier SAR ADC is a good candidate for high-performance low-cost low-power SAR ADC designs.
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