Abstract
This paper presents a self-calibrated least significant bit (LSB) extraction circuitry, which can be used with successive approximation register (SAR) analog-to-digital converters (ADCs) for resolution improvement. The proposed design uses the comparator delay information to increase the resolution by one bit without increasing the internal capacitive digital-to-analog converter resolution or the number of comparisons in one SAR cycle. The reference delay used in the LSB extraction circuitry is generated by the stochastic self-calibration loop to track variations over time. The post-layout simulations show that the proposed design increases the signal-to-noise-and-distortion ratio of the presented 9-bit 200 MS/s SAR ADC in 65 nm CMOS by 3.35 dB with insignificant degradation in power consumption, speed, and area.
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