CMOS Fabrication Research Articles

A low-power single ended half-select free 7 T SRAM cell with improved write margin at 32 nm technology node

Abstract A single-ended single port 7T SRAM bit-cell with a process-variation tolerant architecture and half-select resilience at 32 nm CMOS technology node is presented. The proposed 7 T (7TP) SRAM bit-cell integrates a low threshold voltage (LVTH) feedback cutting transistor along with nominal VTH devices. The reliability of the 7TP cell is presented for process, voltage and temperature (PVT) variations to account for local/global variations incurred during CMOS fabrication. 7TP SRAM bit-cell consistently exhibits 6-σ deviation for static noise margin (SNM), Write Margin (WM) and delay using 1000-point Monte Carlo simulations. The 7TP bit-cell shows improved WM, SNM, power consumption and delay compared to other SRAM cell architectures. The 7TP has the lowest normalized WM-1(WM- 0) of 8.5025%(8.5025%) compared to 17.0150%(46.0875%), 36.5800%(36.5800%), 17.0150%(53.5725%), 53.5450%(14.3650%), 11.8925%(11.8925%) for 7Tn, 7Ti, 7Tj, 8T and 11T SRAM cells respectively. The read-1(read-0) and write-1(write-0) power of the 7TP cell is 887.2 nW(10.09 μW) and 1087 nW(26.6 μW) respectively. The write-1 power of 8 T, 9 T and 10 T cells is 112.2%, 113.70%, and 136.11% of 7TP cell respectively. The proposed cell has the second-best HSNM/RSNM value of 0.269 V at VDD = 0.8 V. The area of the proposed cell is 0.104 sq. μm, the least among other SRAM bit-cells.

Dual-mode 1 × 2 optical switch with simultaneous modulation based on inverse design devices

Abstract Mode division multiplexing (MDM) technology, based on the parallelism inherent in mode dimensions, provides an advancement in enhancing on-chip optical communication channel capacity. In MDM communication systems, the routing and switching of optical signals are of essential importance. However, conventional multimode optical switches typically follow the demultiplexing-processing-multiplexing technological route, leading to an unavoidable increase in device size. In scenarios where multiple modes need to be routed synchronously, the implementation of simultaneous modulation optical switches offers a more efficient and feasible solution. Here, we propose two 1×2 dual-mode optical switches with simultaneous modulation on a silicon-on-insulator (SOI) platform in the 1525-1565 nm wavelength range, utilizing two optical phase modulation techniques: mode transformation and waveguide widening. Simultaneously, we employ inverse design methodologies based on the adjoint variable method (AVM) and level-set method to create the compact single-connected devices, which are compatible with CMOS fabrication processes. The experimental results show that the insertion losses for both TE0 and TE1 modes are less than 1.6 dB (2.5 dB), with the worst modal crosstalk at most -13.5 dB (-12.7 dB) for the switch based on mode transformation (waveguide widening) strategy at the wavelength of 1550nm. The extinction ratio (ER) of the two proposed optical switches exceeds 25 dB at the same wavelength. Furthermore, the switches exhibit a 10%-90% rise time of 15.2 μs and a 90%-10% fall time of 19.5 μs at 1550 nm, indicating the switching speed can be up to kilohertz (kHz). Our proposed 1×2 optical switches hold potential as a fundamental unit for optical signal switching in high-integration multimode optical communication systems.

A transient-enhanced output-capacitorless LDO regulator with non-inverting pull–push gain stage

A novel non-inverting pull–push gain stage output-capacitorless low-dropout regulator (OCL-LDO) is introduced, designed specifically for power management of system-on-chip (SoC). The incorporation of an innovative non-inverting gain stage (NIGS) serves to shift the non-dominant parasitic poles to higher frequencies, thereby enhancing the overall stability of the system. The proposed pull-push configuration markedly improves the slew rate limitation at the gate of the power transistor. Post-layout simulation outcomes, corroborated through a 180-nm CMOS fabrication process, indicate that the proposed LDO regulator maintains stability across a wide range of loading currents, from 0 mA to 100 mA, with a Miller compensation capacitance of only 3.5 pF. The circuit operates with a quiescent current of 143 μA when powered by a 1.5 V single supply. The LDO regulator boasts a dropout voltage of 300 mV, enabling it to deliver up to 100 mA of load current. Simulation results show that the undershoot voltage is only 63.7 mV when the load current jumps from 0 to 100 mA with edge of 100 ns, while employing a 100 pF capacitance load. The recovery time to return to equilibrium post this abrupt change is approximately 0.15 μs. The proposed OCL-LDO regulator exhibits a substantial enhancement in transient response compared to its predecessors, alongside a harmonized balance between line regulation and load regulation performance parameters.

Vertical integration of KTN on SOI wafer

Optical modulators play an important role in communication systems, and silicon has been a focal point in this field thanks to its compatibility with CMOS fabrication. However, silicon’s lack of inherent electro-optic behavior makes it suboptimal for modulation purposes. Conversely, potassium tantalate niobate (KTN) materials boast an improved electro-optic coefficient, presenting a path for improving modulation efficiency. However, limited research exists on KTN materials due to the difficulties associated with their fabrication. Here, a fabrication methodology is described for wafer-scale vertical integration of KTN material onto silicon-on-insulator (SOI) wafers. The resulting devices exhibit a propagation loss of 3.3 dBmm1 and a transition loss within the range of 0.46 to 0.76 dB, which are in agreement with simulations. This method tackles the fabrication challenges and showcases the potential of utilising KTN as the integration material on silicon platform for future optical modulators.

CMOS Compatible Hydrogen Sensor Using Platinum Gate and ALD-Aluminum Oxide.

In this study, a p-Si/ALD-Al2O3/Ti/Pt MOS (metal oxide semiconductor) device has been fabricated and used as a hydrogen sensor. The use of such a stack enables a reliable, industry-compatible CMOS fabrication process. ALD-Al2O3 has been chosen as it can be integrated into the back end of the line (BEOL) or in CMOS, post processing. The device response and recovery are demonstrated with good correlation between the capacitance variation and the hydrogen concentration. Detection down to 20 ppm at 140 °C was obtained and a response time of 56 s for 500 ppm was recorded.

ASIC Design of Low Power Sobel Edge Detection Filter: An Analog Approach

This paper proposes a novel analog front end to filter edges in captured images. The proposed architecture employs the Sobel algorithm and uses a [Formula: see text] kernel to process the input images. We used 180 nm Semi-Conductor Laboratory (SCL) CMOS fabrication technology for implementation with a power supply of 1.8 V. The proposed design employs six analog differential pairs in each horizontal and vertical gradient unit. The inputs to the differential pairs are the active signals fed from the [Formula: see text] kernel using the Sobel weight masks. We connected the differential datum pairs in cascade to estimate the gradient index in horizontal/vertical direction using the net difference current between the output terminals. The horizontal and vertical gradient units, viz., [Formula: see text] and [Formula: see text], respectively, are configured based on the polarity of weights in respective Sobel masks. The gradient [Formula: see text] of the processing pixel (PP) is estimated using the net difference current in the combined circuitry employing [Formula: see text] and [Formula: see text] cells. The key advantages of the proposed design are very low area realization, high accuracy, and low power dissipation. The efficacy of the proposed edge filter analog front end is estimated through simulations and analysis with two sets of test signals in the processing window.

Laser-Assisted Bonding Approach for Photonic Integration Processes

Current development trends concerning miniaturizing of electronics and photonics systems are aiming at assembly and 3D co-integration of a broad range of technologies including MEMS, microfluidics, wafer level optics, and silicon photonics. To this end, on-chip integration using siliconphotonics platform offers a wide range of possibilities addressing passive optics functionality, active optoelectronic devices, and compatibility with CMOS fabrication. On the other hand, the hybrid technology enabling volume manufacturing of such system-on-chip components it is still in an early development stage. In this work, the original LAB setup with a coaxial bottom irradiation architecture was developed. The setup allows a rapid and energy-effective process with the ability to produce successful electrical bonds with negligible thermalinduced stress and warpage to bonded surfaces. The proposed machine-vision based temperature sensor is validated for photonic integration assembly processes.

Low Frequency Noise Behavior in Resistive Memory Devices with Hf/HfO2 Stack

Resistive-random-access-memory (RRAM) devices are considered to be one of the most potential candidates of next generation emerging memory technologies due to their excellent device properties, such as high density, low power, low voltage, and high speed. RRAM features simple metal–insulator–metal (MIM) structures and is fully compatible with traditional CMOS fabrication processes. Low-frequency noise (LFN) measurement is a technique to characterize electrically the trap-assisted conduction processes in dielectrics. In this work, we report the LFN characteristics of Hf/HfO2-based bipolar RRAM and investigate the current conduction mechanism and internal physics.

Investigation of Deuterium De-Passivation by Repetitive Thermal Stress in CMOS Fabrication

Investigation of Deuterium De-Passivation by Repetitive Thermal Stress in CMOS Fabrication

Process and Design Challenges for Hybrid Bonding

Hybrid bonding is one of the key technology to enable solutions for high bandwidth with increasing power and signal integrity. Hybrid bonding involves, face-to-face interconnect formation between wafers and it acts as an extension of fusion bonding technology. Wherein, dielectric materials such as silicon dioxide bond at room temperature and the copper vias embedded in the dielectric expand to form the electrical connections, enabling the interconnect formation between the top and bottom wafer.Hybrid bonding provides advantages over traditional C4 flip-chip bonding involving solder-based micro-bumps, such as, interconnect pitch scaling to less than 10 µm thereby providing higher interconnect density and increased power and signal speed efficiency for memory and high-performance computing application along with better reliability. It is compatible with standard CMOS fabrication technology.In this work, we would like to present the design and process challenges which may lead to improved bonding yield. To enable hybrid bonding with high yield it is necessary that the bonding surfaces are flat with low roughness. The optimized chemical mechanical polishing (CMP) process is one of the key process technology which enables surface topography to be less than 10 nm and surface roughness to be less than 0.8 nm. The surface topography is dependent on the metal via layout, interconnect density and the surrounding dielectrics and hence, these design parameters act as a guiding principle for the application-oriented definition of the design to accommodate different pitch sizes of interconnecting vias (from 1 µm to 10 µm). The mechanical properties of the materials play a key role as well as this will define the removal rate of dielectric and the metals during the CMP process which will affect the dishing and the surface topography. To achieve high bonding yield the surface topography is key as this will affect the bond front propagation and hence the bonded and non-bonded region between the dielectrics. To further improve the bonding yield we have applied a tailored annealing recipe which improves the bonding yield significantly. This paper would focus our work on topography improvement and overall bonding yield in detail and a comparison of bonding yield with and without dummy vias. Dummy vias in this context refer to the copper via structures that are not intended for interconnect formation but are there for CMP process optimization to achieve better process control. Hence, the dummy vias are not connected to the underlying routing metal layer.Figure 1, shows an ideal surface that would result in W2W bonding with high yield. Figure 2 shows, the defects such as high copper dishing, copper protrusion, dielectric erosion and poor surface topography which will result in poor bonding yield. Figure 3 shows the bonding using SiON as the bonding dielectric with (a) without dummy copper vias (~98% bond yield) and (b) with dummy copper vias (~88% bond yield). Figure 1

Low-temperature deuterium annealing for improved electrical characteristics of SONOS

Deuterium annealing is a promising process technology for CMOS fabrication. Deuterium annealing effectively passivates interface traps at the Si-SiO2 interface, allowing for improvements in the electrical characteristics and reliability of CMOS. However, conventional deuterium annealing is typically performed at high temperatures above 400 °C, which can lead to unwanted dopant deactivation, random dopant fluctuation (RDF), and thermal-induced stress in the backend-of-the-line (BEOL). In this study, we demonstrate the use of deuterium annealing at low temperatures, resulting in improvements in SONOS devices. Device characterizations based on subthreshold swing (SS), on-state current (ION), off-state current (IOFF), and gate leakage current (IG), as well as time-of-flight secondary ion mass spectrometry (ToF-SIMS) are included to clarify the effects of annealing.

Review: tunable nanophotonic metastructures.

Tunable nanophotonic metastructures offer new capabilities in computing, networking, and imaging by providing reconfigurability in computer interconnect topologies, new optical information processing capabilities, optical network switching, and image processing. Depending on the materials and the nanostructures employed in the nanophotonic metastructure devices, various tuning mechanisms can be employed. They include thermo-optical, electro-optical (e.g. Pockels and Kerr effects), magneto-optical, ionic-optical, piezo-optical, mechano-optical (deformation in MEMS or NEMS), and phase-change mechanisms. Such mechanisms can alter the real and/or imaginary parts of the optical susceptibility tensors, leading to tuning of the optical characteristics. In particular, tunable nanophotonic metastructures with relatively large tuning strengths (e.g. large changes in the refractive index) can lead to particularly useful device applications. This paper reviews various tunable nanophotonic metastructures' tuning mechanisms, tuning characteristics, tuning speeds, and non-volatility. Among the reviewed tunable nanophotonic metastructures, some of the phase-change-mechanisms offer relatively large index change magnitude while offering non-volatility. In particular, Ge-Sb-Se-Te (GSST) and vanadium dioxide (VO2) materials are popular for this reason. Mechanically tunable nanophotonic metastructures offer relatively small changes in the optical losses while offering large index changes. Electro-optically tunable nanophotonic metastructures offer relatively fast tuning speeds while achieving relatively small index changes. Thermo-optically tunable nanophotonic metastructures offer nearly zero changes in optical losses while realizing modest changes in optical index at the expense of relatively large power consumption. Magneto-optically tunable nanophotonic metastructures offer non-reciprocal optical index changes that can be induced by changing the magnetic field strengths or directions. Tunable nanophotonic metastructures can find a very wide range of applications including imaging, computing, communications, and sensing. Practical commercial deployments of these technologies will require scalable, repeatable, and high-yield manufacturing. Most of these technology demonstrations required specialized nanofabrication tools such as e-beam lithography on relatively small fractional areas of semiconductor wafers, however, with advanced CMOS fabrication and heterogeneous integration techniques deployed for photonics, scalable and practical wafer-scale fabrication of tunable nanophotonic metastructures should be on the horizon, driven by strong interests from multiple application areas.

Reconfigurable Generation of PAM-4 Signal Based on Fano Effect for Optical Interconnect Systems

We present a novel low-power architecture for the generation of multilevel pulse amplitude modulation (PAM-4) signal generation. A new structure of a micro-ring resonator based on a 4´4 MMI (Multimode interference) coupler is proposed to control the coupling coefficient and Fano shapes. Based on this structure, a high linearity of the transmission is created, compared with the Mach Zehnder Interferometer (MZI) conventional structure. Here, instead of using directional couplers and MZI as shown in the previous reports, in our method only two 4´4 multimode interference structures on silicon on insulator (SOI) waveguides has been used. The new design is compatible and suitable for the current CMOS fabrication technology. In this work, the special design is as follows: one of two MMI couplers is used to be a micro-ring resonator and two segmented phase shifters are used in the micro-ring resonator to generate 4 levels of the PAM-4 signal. The micro-ring resonator is controlled to work at the over-coupled region, so the Fano effect can be generated. This proposed PAM-4 architecture uses the generated Fano effect, therefore an extreme reduction in power consumption can be achieved. A large fabrication tolerance of ±500 nm and a compact footprint of 10´500 µm2 can be carried-out. The device is simulated and optimally designed using the FDTD (finite difference time domain) and EME (Eigenmode Expansion). This architecture can be useful for optical interconnects and data center network applications.

Material to system-level benchmarking of CMOS-integrated RRAM with ultra-fast switching for low power on-chip learning

Analog hardware-based training provides a promising solution to developing state-of-the-art power-hungry artificial intelligence models. Non-volatile memory hardware such as resistive random access memory (RRAM) has the potential to provide a low power alternative. The training accuracy of analog hardware depends on RRAM switching properties including the number of discrete conductance states and conductance variability. Furthermore, the overall power consumption of the system inversely correlates with the RRAM devices conductance. To study material dependence of these properties, TaOx and HfOx RRAM devices in one-transistor one-RRAM configuration (1T1R) were fabricated using a custom 65 nm CMOS fabrication process. Analog switching performance was studied with a range of initial forming compliance current (200–500 µA) and analog switching tests with ultra-short pulse width (300 ps) was carried out. We report that by utilizing low current during electroforming and high compliance current during analog switching, a large number of RRAM conductance states can be achieved while maintaining low conductance state. While both TaOx and HfOx could be switched to more than 20 distinct states, TaOx devices exhibited 10× lower conductance, which reduces total power consumption for array-level operations. Furthermore, we adopted an analog, fully in-memory training algorithm for system-level training accuracy benchmarking and showed that implementing TaOx 1T1R cells could yield an accuracy of up to 96.4% compared to 97% for the floating-point arithmetic baseline, while implementing HfOx devices would yield a maximum accuracy of 90.5%. Our experimental work and benchmarking approach paves the path for future materials engineering in analog-AI hardware for a low-power environment training.

Photonic Integrated Circuit Based Temperature Sensor forOut-of-Autoclave Composite Parts Production Monitoring.

The use of composite materials has seen widespread adoption in modern aerospace industry. This has been facilitated due to their favourable mechanical characteristics, namely, low weight and high stiffness and strength. For broader implementation of those materials though, the out-of-autoclave production processes have to be optimized, to allow for higher reliability of the parts produced as well as cost reduction and improved production speed. This optimization can be achieved by monitoring and controlling resin filling and curing cycles. Photonic Integrated Circuits (PICs), and, in particular, Silicon Photonics, owing to their fast response, small size, ability to operate at higher temperatures, immunity to electromagnetic interference, and compatibility with CMOS fabrication techniques, can offer sensing solutions fulfilling the requirements for composite material production using carbon fibres. In this paper, we demonstrate a passive optical temperature sensor, based on a 220 nm height Silicon-on-Insulator platform, embedded in a composite tool used for producing RTM-6 composite parts of high quality (for use in the aerospace industry). The design methodology of the photonic circuit as well as the experimental results and comparison with the industry standard thermocouples during a thermal cycling of the tool are presented. The optical sensor exhibits high sensitivity (85 pm/°C), high linearity (R2 = 0.944), and is compatible with the RTM-6 production process, operating up to 180 °C.

High-Directionality Silicon Nitride Antenna Based on Distributed Bragg Reflector for Optical Phased Array

Optical phased arrays (OPAs) have great potential in the fields of integrated solid-state light detection and ranging. The ranging distance of an OPA can be further enlarged by improving the directionality of the grating antenna. A high-directionality silicon nitride grating antenna with a distributed Bragg reflector (DBR) is proposed. The DBR consists of a stack of silicon nitride and silicon dioxide layers, which are utilized as the bottom reflectors to further reduce downward radiation. In a simulation, the directionality of the antenna exceeded 71.6% within the wavelength range of 1420–1740 nm. Additionally, the directionality of the antenna can achieve 97.6% at 1550 nm. Compared to a grating antenna without a DBR, the directionality is improved by 1.52 dB. Moreover, the proposed silicon nitride grating antenna has a large fabrication tolerance and is compatible with CMOS fabrication techniques, showing great potential for enhancing the performance of the integrated optical phased array.

Full CMOS Circuit for Brain-Inspired Associative Memory With On-Chip Trainable Memristive STDP Synapse

Spiking neural networks (SNNs) implemented in neuromorphic computing architectures promise a high degree of bio-plausibility and energy efficiency compared to the artificial neural network (ANN). Thus, SNN-based spiking associative memories are preferred for high capacity, area, and energy-efficient neural associative memories (NAMs). While most previously published works focused on ANN-based NAM, this work implements the full CMOS circuit of memristor crossbar-based spiking NAM for the first time. Instead of using any software-based memristive SPICE model or memristive devices that are yet not available in standard CMOS technology process design kits (PDKs), in our work, the CMOS-based memristive synapse circuit is employed to address practical circuit implementation challenges. The complete on-chip learning of the system is demonstrated using the bio-plausible spike-timing-dependent plasticity (STDP) learning mechanism without employing any external coprocessor, e.g., microprocessor, field-programmable gate array (FPGA). The entire system is implemented at the transistor level using 180-nm standard CMOS technology to demonstrate the pattern recognition application. The robustness of the proposed circuit is also evaluated to demonstrate the tolerance against the CMOS fabrication non-idealities.

Multimode optical phased array for parallel beam steering - feasibility study.

Silicon integrated Optical Phased Arrays (OPA) have been widely studied for wide and accurate beam steering applications, taking advantage of the high power handling capability, the stable and precise optical beam control, and the CMOS fabrication compatibility to realize low-cost devices. Both one-dimensional and two-dimensional silicon integrated OPAs have been demonstrated, and beam steering over a large angular range with versatile beam patterns have been achieved. However, existing silicon integrated OPAs are based on single mode operation, tuning the phase delay of the fundamental mode amongst phased array elements and generating a beam from each OPA. Whilst generating more beams for parallel steering are feasible by using multiple OPAs integrated on the same silicon circuit, the device size, complexity as well as power consumption increase substantially. To overcome these limitations, in this research, we propose and demonstrate the feasibility of designing and using multimode OPA to generate more than one beam from the same silicon integrated OPA. The overall architecture, multiple beam parallel steering operation principle, and key individual components are discussed. Results show that with the simplest two modes operation, the proposed multimode OPA design principle can realize parallel beam steering to reduce the number of beam steering required over the target angular range and the power consumption by almost 50%, whilst minimizing the device size by more than 30%. When the multimode OPA operates with a larger number of modes, the improvements on the number of beam steering, the power consumption and the size increase further.

Multi-element metasurface system for imaging in the near-infrared

Metasurfaces are optically thin 2D arrays of subwavelength scatterers that modify scalar and vector properties of incident electromagnetic fields. Metasurface lenses are of particular interest for imaging applications for their flat form factor, compatibility with CMOS fabrication processes, and potential for correcting aberrations with a small number of elements. We advance this capability by realizing a millimeter-diameter, polarization-independent metalens triplet system with chromatic aberration correction over the wavelength range of 1.30–1.60 μm and monochromatic aberration correction enabling a field of view of 50°.

A New Look at Silicon Carbide

Silicon Carbide, SiC is one of the most widely used materials that plays a critical role in industries such as: aerospace, electronics, industrial furnaces and wear-resistant mechanical parts among others. Although SiC is widely used in electronics and other high technology applications, the metallurgical, abrasive, and refractory industries are dominate by volume. It is only in the last five or six years that SiC has gained a new and important role in the semiconductor industry. SiC has become a key material in the drive towards electrification. It’s unique physical properties, wide band gap, especially, high temperature performance and “ease of manufacturability makes it a key material going forward. The physical properties that make SiC so unique also represent some serious problems to large scale manufacturing of SiC diodes, transistors and modules. SiC is a very tough material, it has a Mohs hardness rating of 9.5 approaching that of diamond. Just as the semiconductor industry needed high quality defect free silicon wafers to move forward, so did the SiC industry. High quality defect free wafers have just come into the market. They are 4 and six wafers that will allow SiC. These boules can be “sliced” in wafers and run on a standard CMOS fabrication process. Next comes the dicing of the wafers into devices. A diamond saw has to be run at a very slow rate to a material almost as hard as the diamond itself. Die attach brings an interesting problem the devices are generally rate at 200+ deg C and voltages >1000W. Standard epoxy and even Au/Si eutectic die attach has issues has issues at these extreme operating conditions. Lastly, the epoxy molding compound has to be capable of withstanding the harsh conditions and not breakdown. These are all challenges that are being met today. This is a continuing story of how the semiconductor industry adapts to ever changing requirements