Full CMOS Circuit for Brain-Inspired Associative Memory With On-Chip Trainable Memristive STDP Synapse

Abstract

Spiking neural networks (SNNs) implemented in neuromorphic computing architectures promise a high degree of bio-plausibility and energy efficiency compared to the artificial neural network (ANN). Thus, SNN-based spiking associative memories are preferred for high capacity, area, and energy-efficient neural associative memories (NAMs). While most previously published works focused on ANN-based NAM, this work implements the full CMOS circuit of memristor crossbar-based spiking NAM for the first time. Instead of using any software-based memristive SPICE model or memristive devices that are yet not available in standard CMOS technology process design kits (PDKs), in our work, the CMOS-based memristive synapse circuit is employed to address practical circuit implementation challenges. The complete on-chip learning of the system is demonstrated using the bio-plausible spike-timing-dependent plasticity (STDP) learning mechanism without employing any external coprocessor, e.g., microprocessor, field-programmable gate array (FPGA). The entire system is implemented at the transistor level using 180-nm standard CMOS technology to demonstrate the pattern recognition application. The robustness of the proposed circuit is also evaluated to demonstrate the tolerance against the CMOS fabrication non-idealities.