CMOS Fabrication Research Articles

High-Performance Radiation-Hardened Spintronic Retention Latch and Flip-Flop for Highly Reliable Processors

Radiation vulnerability and high power density are critical challenges in modern CMOS processors. Spin-based devices like magnetic tunnel junction (MTJ) are among the promising alternatives for addressing these challenges thanks to their fascinating properties such as radiation immunity, non-volatility, high endurance, and compatibility with the CMOS fabrication process. Utilizing the fascinating non-volatile property of the MTJ device, a high-performance, and energy-efficient soft error immune retention latch, and a high-reliable non-volatile flip-flop (FF) are proposed in this paper. Thanks to the single event upset (SEU) immunity, the proposed circuits are applicable in designing highly reliable processors, especially in applications like aerospace systems, where immunity to radiation induced soft errors is very critical. Because of the innovative design of the proposed approach, the MTJ switching delay does not affect the performance of the proposed latch. The simulation results indicate that the proposed latch offers lower delay, power consumption, and power delay product (PDP) than the state-of-the-art designs. The results of the comprehensive Monte-Carlo simulations also demonstrate that the proposed approach is more robust to process, voltage, and temperature variations as compared to their previous counterparts. This is because our designs do not use a pre-charge sense amplifier (PCSA) to read the data stored in the MTJs, and hence, the proposed designs have lower error rates. Furthermore, the transient impact of the particle strikes on the internal nodes is not transferred to the output node of the proposed circuits. The proposed design also has a significantly shorter output recovery time compared to its state-of-the-art counterparts.

A novel tunable bandgap voltage and current reference generation circuit

This paper presents a CMOS based tunable bandgap voltage and current reference generation circuit. The proposed circuit is designed without using Bipolar Junction Transistors (BJTs) for Proportional-To-Absolute-Temperature and Complementary-To-Absolute-Temperature generation, thus eliminating the problem of implementing BJT in CMOS fabrication process. The proposed circuit is simulated in standard 180 nm CMOS technology. A constant reference voltage ( $$V_{ref}$$ ) from 850 mV to 1.14 V and a constant reference current ( $$I_{ref}$$ ) from 170 to 227 nA is generated for corresponding supply voltage ( $$V_{dd}$$ ) tuned from 1.5 to 2 V for low power applications with an extended temperature range from − 55 to 175 $$^{\circ }$$ C. The proposed circuit at $$V_{dd}$$ = 1.8 V has a Temperature Coefficient (TC) of 0.37 and 0.53 ppm/ $$^{\circ }$$ C for $$V_{ref}$$ and $$I_{ref}$$ respectively, with a total power consumption of 594 nW (at $$V_{ref}$$ = 1.02 V and $$I_{ref}$$ = 204.5 nA). A monte-carlo simulation of the design is done for 1000 samples. The monte-carlo simulation for $$\hbox {V}_{{ref}}$$ , $$\hbox {I}_{{ref}}$$ and TC is done across the $$\hbox {V}_{{dd}}$$ (i.e. $$\hbox {V}_{{dd}} = 2\,\hbox {V}$$ to 1.5 V).

Sensitivity Improvement of a Fully Symmetric Vertical Hall Device Fabricated in 0.18 μm Low-Voltage CMOS Technology

This paper proposes a new implementation method to significantly improve the magnetic sensitivity of a fully symmetric vertical Hall device (FSVHD) based on low-voltage CMOS technology. The FSVHD consists of four identical three-contact vertical Hall elements (3CVHE) and each 3CVHE is located in a low-doped deep n-well. The terminals of the 3CVHE are $\text{n}^{+}$ implanted in an n-well and a $\text{p}^{+}$ implantation in a p-well is performed to act as a trench between two adjacent $\text{n}^{+}$ contacts, enabling Hall current flowing deeply for sensitivity improvement. The influence of the geometry sizes on magnetic sensitivity is exploited utilizing TCAD simulation to obtain the optimized device structure in a $0.18~\mu\text{m}$ CMOS standard technology. The experimental results reveal that the proposed FSVHD with a $\text{p}^{+}$ /p-well trench can attain an improved voltage-related sensitivity of 8.4 mV/VT, which is about 70% higher than that of a conventional FSVHD without a trench in the same CMOS fabrication process, while offset and noise are not degraded. The proposed $\text{p}^{+}$ /p-well implantation trench is a good solution to enhance the sensitivity of a low-voltage CMOS VHD with a low manufacturing cost.

Visible and Near-IR Nano-Optical Components and Systems in CMOS

Integration of complex optical systems operating in the visible and near-IR range, realized in a CMOS fabrication process with an absolutely ‘no change’ approach, can have a transformative impact in enabling a new class of miniaturized, low-cost, smart optical sensors and imagers for emerging applications. While ‘silicon photonics’ has demonstrated the path towards such advancements in the IR regime, the field of VIS/NIR integrated optics has seen less progress. Therefore, while currently ultra high-density and higher performance image sensors are commonplace in CMOS, all passive optical components (such as lenses, filters, gratings, collimators) that typically constitute a high-performance sensing or imaging system, are typically non-integrated, bulky and expensive, severely limiting their application potential in the space of connected sensors. Here, we present an approach to utilize the embedded copper-based metal interconnect layers in modern CMOS processes with sub-wavelength feature sizes to realize multi-functional nano-optical structures and components. Based on our prior works, we illustrate this electronic-photonic co-design approach exploiting metal/light interactions and integrated electronics in the 400nm-900 nm wavelengths with three design examples. Realized in 65-nm CMOS, these demonstrate for the first time: fully integrated multiplied fluorescence based biosensors with integrated filters, optical spectrometer, and CMOS optical physically unclonable function (PUF). These examples cover a range of optical processing elements in silicon, from deep sub-wavelength nano-optics to diffractive structures. We will demonstrate that when co-designed with embedded photo-detection and signal processing circuitry, this approach can foster millimeter-scale, intelligent optical sensors for a wide range of emerging applications in healthcare, diagnostics, smart sensing, food, air quality, environment monitoring and others.

Carrier depletion type PIN phase shifter in silicon MZM for 200 Gbps operation

Silicon-based photonic modulators are a primary choice for on-chip optical devices with CMOS fabrication compatibility. The phase shifter in a silicon photonics modulator plays a significant role in determining the efficiency of the modulator to meet the optical data communication's future demands. Obtaining high extinction ratio (ER) and with acceptable bit error rate (BER) at low voltage and low loss was kept as the primary objective for the proposed PIN phase shifter in an unbalanced silicon Mach-Zehnder modulator. The phase shifter length was kept at 2 mm, and the carrier doping region was reduced to decrease the carrier absorption loss. The concentration of P and N in the phase shifter was set to 7 × 1017 cm−3 and 5 × 1017 cm−3, and the intrinsic gap was varied (50, 100, 150, 200, 250, 300, 350 and 450 nm) for the study to obtain the optimum gap to meet the objective. For 200 Gbps, the proposed modulator with intrinsic gap 150 nm obtained 18.68 dB ER having VπL = 0.8 V.cm. Insertion loss obtained for the phase shifter was 3.421 dB/cm. The proposed design is expected to enhance the performance of silicon optical modulators for commercial applications, and also other applications such as optical switches, delay lines, and optical interconnect.

Electrostatic and Dynamic Analysis of P+PNP Double Junction Type and P+PNPN Triple Junction Type Pinned Photodiodes

This paper explains the device structure and operation of image sensors and solar cells. Both are semiconductor devices operating with the same physical principle of detecting photons. A high efficiency of the photon to electron energy conversion is very much desired in both devices. Image sensors now use a very advanced and scaled down CMOS fabrication process technology to achieve high performance features such as the excellent short wave blue light sensitivity for good color reproduction, the low noise and the no image lag picture quality for filmless and mechanical free action cameras. On the other hand, solar cells are still now built with the primitive floating N+P single junction type photodiode to minimize the fabrication process cost but with very low energy conversion efficiency of about 20%. It is explained in details that the depletion region of the PN junction is not the only place where we can achieve photo electron and hole pair separations effectively. The short-wave blue light has only 1000 Å silicon crystal penetration depth. The pinned surface P+P Gaussian doping profile has a very important role to achieve a better photon to energy conversion efficiency, especially for the short-wave blue light. Electrostatic and dynamic behaviors of Pinned Surface P+PNP Double Junction type Dynamic Photo Transistor and Pinned Surface P+PNPN Triple Junction type Dynamic Photo Thyristor are analyzed in details. Both of them are shown to be expected to have much excellent photon-to-electron energy conversion efficiency.

(Invited) Si-Cap-Free Low-DIT SiGe Gate Stack for High-Performance pFETs

As the continuous physical device scaling is facing increasing challenges in today’s CMOS technology, introduction of high mobility channel material has further increased its potential value as performance booster. Low-Ge-content SiGe is the leading candidate for p-channel devices, as it is process-compatible with state-of-the-art Si CMOS fabrication platform and requires no strain relaxed buffer layer. In order to benefit from the high intrinsic carrier mobility at a low VDD operation, an efficient SiGe channel passivation with low interface state densities (Dit) needs to be developped. However, the presence of GeO is known to increase Dit [1]. One of the effective passivation schemes for SiGe-based channel surface uses an epitaxially-grown ultrathin Si cap [2]. It suppresses the formation of GeO and enables to fabricate a high-k/SiO2 gate stack equivalent to the one in Si devices. The outstanding improvement achieved with this approach was previously highlighted on pure Ge channel devices, where the formation of GeO is inevitable without the use of Si-cap [3]. On the other hand, it poses some concerns such as EOT penalty and process controllability, making the Si-cap-free route the desired option as long as the interface and oxide bulk trap densities can be kept under control. In this contribution, we will review our recent studies towards the realization of a low-Dit Si-cap-free SiGe gate stack [4]. Selective GeO scavenging from Si1-xGexOy interface layer was previously reported as the key process to reduce Dit of SiGe gate stack [1]. Wostyn et al., demonstrated on Si0.75Ge0.25 that the annealing of chemical oxide in inert ambient (i.e. H2) reduces GeO in Si1-xGexOy IL thanks to the conversion of the thermally-unstable GeO into SiO [5]. A MOS capacitor experiment confirmed a clear Dit reduction by H2 anneal, although at an increased EOT. Additional NH3 anneal on IL was found to further reduce the Dit down to 5×1011 cm-2eV-1 while cancelling out the H2-anneal-induced EOT increase (EOT=10.1 Å). We also found that the metal gate deposition process has a strong impact on Dit even for the same metal. While the PVD W/TiN led to low Dit and EOT, both of them increased as the PVD was changed to ALD (or ALD followed by CVD) process. This can be explained by the PVD-TiN-induced additional GeO scavenging from IL [6] and/or oxygen diffusion from ALD-based metal to IL through HfO2 inducing GeO formation. A nitridation of HfO2 was found to suppress the negative impact from ALD-based metal electrode. XPS confirmed that the significant Dit reduction coincides with the nitridation of HfO2. By replacing the HfO2 with other dielectrics in which lower oxygen diffusivity is expected such as SiO2, the Dit of SiGe gate stack became insensitive to the metal deposition process and nitridation, indicating that the high oxygen diffusivity of the HfO2 layer was, together with the GeO formation, the root cause of the process-sensitive Dit. These results emphasize the importance of the oxygen depth profile control for the realization of a low-Dit SiGe gate stack.

Electrically driven acousto-optics and broadband non-reciprocity in silicon photonics

Emerging technologies based on tailorable interactions between photons and phonons promise new capabilities ranging from high-fidelity microwave signal processing to non-reciprocal optics and quantum state control. While such light-sound couplings have been studied in a variety of physical systems, many implementations rely on non-standard materials and fabrication schemes that are challenging to co-implement with standard integrated photonic circuitry. Notably, despite significant advances in integrated electro-optic modulators, related acousto-optic modulator concepts have remained relatively unexplored in silicon photonics. In this article, we demonstrate direct acousto-optic modulation within silicon waveguides using electrically-driven surface acoustic waves (SAWs). By co-integrating SAW transducers in piezoelectric AlN with a standard silicon-on-insulator photonic platform, we harness silicon's strong elasto-optic effect to mediate linear light-sound coupling. Through lithographic design, acousto-optic phase and single-sideband amplitude modulators in the range of 1-5 GHz are fabricated, exhibiting index modulation strengths comparable to existing electro-optic technologies. Extending this traveling-wave, acousto-optic interaction to cm-scales, we create electrically-driven non-reciprocal modulators in silicon. Non-reciprocal operation bandwidths of >100 GHz and insertion losses <0.6 dB are achieved. Building on these results, we show that unity-efficiency non-reciprocal modulation, necessary for a robust acousto-optic isolator, is within reach. The acousto-optic modulator design is compatible with both CMOS fabrication and existing silicon photonic device technologies. These results represent a promising new approach to implement compact and scalable acousto-optic modulators, frequency-shifters, and non-magnetic optical isolators and circulators in integrated photonic circuits.

(Invited) Theory of Silicon-Based Light Emitting

The indirect band gap preclude the silicon from making light-emitting devices, which is, however, a quest for exploration of large-scale integration of both electronic and photonic devices on a single microchip. Why silicon and germanium are both indirect band gap and most of group III-V and all group II-VI semiconductors are direct band gap is a long standing puzzle. In this talk, I will first present our recently developed unified theory, based on occupied d orbitals in cations, for explaining why diamond, Si, Ge, and Al-containing group III-V semiconductors have indirect band gap, and the remaining group III-V and II-VI semiconductors, except GaP, have direct band gap. This theory also unravels that it is impossible to make allotropes of Si and compounds consisting by Si mixed together with other elements high efficient direct bandgap light emitting. Interface and quantum confinement in low-dimensional Si nanostructures are two knobs to relax the momentum conservation law of optical transition. Our theory confirms that the light emission efficiency of Si quantum dots increases exponentially as reducing dot size, but its highest reachable efficiently is still two orders of magnitude smaller than that of direct bandgap InP and GaAs. Fortunately, we discovered that Si/Ge magic sequence superlattices exhibit orders more efficient at emission light than their existing counterpart records and approach more than 10% brightness of real direct gap materials, such as GaAs. Furthermore, regarding the direct bandgap is only 140 meV above the indirect bandgap in Germanium (Ge), it is well established that a tiny (1-2%) extensile strain could render an indirect-to-direct bandgap transition and makes it direct bandgap. However, there is no feasible way to create such extensive strain on Ge since the lattice parameter of Ge is even 4.3% larger than Si. We propose insert external atoms into interstitial sites of Ge, which grows on Si substrate through SiGe buffer layer, to induce an effective tensile uniaxial strain on Ge, a new pathway toward direct band gap Ge. Because our proposed scheme is highly compatible with CMOS fabrication process, our presented new pathway would be a solution for on-chip lasers.

(Invited) Theory of Silicon-Based Light Emitting

Why silicon and germanium are both indirect band gap and most of group III-V and all group II-VI semiconductors are direct band gap is a long standing puzzle. In this talk, I will first present our recently developed unified theory to explain why diamond, Si, Ge, and Al-containing group III-V semiconductors have indirect band gap, and the remaining group III-V and II-VI semiconductors, except GaP, have direct band gap. We excluded Si QDs as a candidate for on-chip lasers. We also discovered that Si/Ge magic sequence superlattices exhibit orders more efficient at emission light than their existing counterpart records and approach more than 10% brightness of real direct gap materials, such as GaAs. We further propose to insert external atoms into interstitial sites of Ge to induce an effective tensile uniaxial strain on Ge toward direct band gap Ge. This scheme is highly compatible with CMOS fabrication process.

Proposal for an integrated silicon-photonics terahertz gas detector using photoacoustics.

A design and multiphysical model is presented for an on-chip gas sensor that transduces terahertz gas absorption through sound generation into a mechanical motion that can be read out externally. The signal is triply enhanced by designing a structure that functions simultaneously as an optical, an acoustical and a mechanical resonator. The structure is made in high-resistivity silicon and can be fabricated using CMOS and MEMS fabrication technologies. The sensor is a purely passive element, so an external THz source and read-out are required. The chip has a footprint of 3 mm2. A detection limit of 234 ppb of methanol for a source power of 1 mW and an integration time of 1 ms is predicted.

Using Smart Routing for Secure and Dependable NoC-Based MPSoCs

The Internet-of-Things (IoT) boosted the building of computational systems that share computation, communication and storage resources for uncountable types of applications. MultiProcessor System-on-Chip (MPSoC) is a fundamental component of such systems offering large parallelism degree in an ocean of processors and memories connected through one or more Network-on-Chips (NoCs). Therefore, a massive quantity of sensitive information of several applications can share computation and communication resources of the MPSoCs demanding security mechanisms and policies. Besides, the advances of CMOS technologies increases the quantity of static and dynamic faults, requiring a dependable and resilient target architecture, which can be partially fulfilled by an effective and efficient NoC design. This work addresses fault tolerance and security at NoC level with SDR, a routing algorithm that includes the concept of security zones in the MPSoC while providing support for dependable routing avoiding faulty links. The proposed routing algorithm prioritizes communication paths deemed secure in 2D mesh NoCs with deadlock freedom. Experimental results employing realistic workload scenarios based on the NASA Numeric Aerodynamic Simulation (NAS) Parallel Benchmark (NPB) and a fault model for 65nm and 22nm CMOS fabrication technologies demonstrates the scalability, security, and dependability of SDR.

(Invited) Development of CMOS-MEMS Cointegrated Pressure Sensor Using Minimal Fab Process

The Minimal Fab concept was proposed in 2008 to produce low-volume customized devices with a low investment cost [1]. The different points of Minimal Fab compared with those of the conventional Mega Fab are as follows. (a) Wafer size is half-inch (12.5 mm), (b) the transferring and processing of the wafer are performed with a cleanliness level identical to that of a super clean room, and (c) the machine used compact dimensions of 144 cm height, 30 cm width, and 45 cm depth. Since the proposal of the Minimal Fab concept, many Minimal Fab machines and Minimal Fab processes have been developed actively for the fabrication of CMOS integrated circuits [2, 3]. However, the Minimal Fab process for MEMS sensor fabrications has not been developed sufficiently. In this work, we develop the CMOS-MEMS cointegrated process using the Minimal Fab deep-RIE and mask aligner. By using the developed process, we also fabricate and characterize the digital type CMOS-MEMS pressure sensor. The pressure sensing element in the CMOS-MEMS pressure sensor is the CMOS ring oscillator with the longitudinal PMOSFETs located at the edge areas of a thin circular diaphragm. In the device fabrication, we used (100) oriented half-inch SOI wafers, and the source-drain (SD) regions of the MOSFETs were patterned along with the <110> direction to effectively utilize mechanical stress induced drain current variations. As the gate material, we used a 30-nm-thick PVD-TiN layer to obtain a suitable logic gate threshold voltage of the CMOS invertors. The circular diaphragm was fabricated using Minimal Fab mask aligner and deep-RIE. It was confirmed that the oscillation frequency changes from 360 to 400 kHz by changing pressures from -40 to +40 kPa in the fabricated CMOS-MEMS cointegrated pressure sensor chip. The developed CMOS-MEMS pressure sensor is suitable for the application to the battery drive IoT sensor systems owing to its low power consumption. [1] S. Hara et al., J. Jpn. Precis. Eng., vol. 77, no. 3, p. 249, 2011. [2] Y. X. Liu et al., Jpn. J. Appl. Phys. 56, p. 06GG01-1. [3] Y. X. Liu et al., J. Appl. Phys. 57, p. 06HD03-1.

Temperature Dependence of the Steering Angles of a Silicon Photonic Optical Phased Array

Silicon photonic optical phased arrays leveraging from the well established CMOS fabrication process have become promising candidates to realize miniaturized beam steering systems. While different implementations of optical phased arrays have been successfully demonstrated, no investigations on the influence of thermal distortions on the response of these systems have been performed so far. Due to the high thermo-optic coefficient of silicon, the refractive index and thus the functionality of silicon photonic components depend strongly on the temperature. In highly integrated systems, consisting of several photonic components, in which laser sources and control electronics are directly integrated on top of the photonic IC, heat dissipated by active components leads to temperature gradients and offsets, affecting the functionality of the photonic system. Optical phased arrays consisting of an array of phase sensitive components, are particularly sensitive towards temperature. Therefore, precise investigations of the temperature dependence of the OPA functionality are required. This article aims to expand the understanding of the influence of thermal distortions on the steering angles of optical phased arrays. Thereto, analytical expressions describing the temperature dependence of the steering angles are provided and experimentally validated. The expressions are provided in a general form so that they can be applied to any OPA system regardless of its implementation.

A Silicon Photonic Data Link with a Monolithic Erbium-Doped Laser

To meet the increasing demand for data communication bandwidth and overcome the limits of electrical interconnects, silicon photonic technology has been extensively studied, with various photonics devices and optical links being demonstrated. All of the optical data links previously demonstrated have used either heterogeneously integrated lasers or external laser sources. This work presents the first silicon photonic data link using a monolithic rare-earth-ion-doped laser, a silicon microdisk modulator, and a germanium photodetector integrated on a single chip. The fabrication is CMOS compatible, demonstrating data transmission as a proof-of-concept at kHz speed level, and potential data rate of more than 1 Gbps. This work provides a solution for the monolithic integration of laser sources on the silicon photonic platform, which is fully compatible with the CMOS fabrication line, and has potential applications such as free-space communication and integrated LIDAR.

Configurable Logic Blocks and Memory Blocks for Beyond-CMOS FPGA-Based Embedded Systems

Field programmable gate arrays (FPGAs)-based embedded systems are easy to implement, reconfigure, test, and validate. Configurable logic blocks (CLBs) and memory blocks are the building blocks of FPGA. The rising issues in CMOS fabrication at smaller nanometer levels has increased the need for beyond-CMOS technologies to build complex circuits at extremely smaller nanometer levels. Quantum-dot cellular automata (QCA) is a nascent beyond-CMOS nanotechnology technique to design low-power and high-performance digital circuits. In this letter, a layout strategy is proposed to design QCA circuits. Using the proposed strategy, novel and cost-efficient designs of CLBs and memory blocks are proposed. The proposed blocks can be used to develop FPGA architecture and FPGA-based embedded systems in QCA. The proposed circuits are cost effective and perform better than many state-of-the-art designs. Simulation and verification are done in QCADesigner using coherence vector simulation engine.

Luminescence Mechanism in Amorphous Silicon Oxynitride Films: Band Tail Model or N-Si-O Bond Defects Model

Silicon oxynitride films are one kind of important gate dielectric materials for applications in the fabrication of silicon CMOS integrated circuits (ICs), which have been widely and deeply studied. However, with the significant demand of the technologies for Si-based monolithic optoelectronic ICs, the research efforts on the optoelectronic applications of these materials have been continually increasing, particularly in the study of light emission properties and recombination mechanisms. In this paper, we first briefly outline the present photoluminescence (PL) mechanisms in amorphous silicon oxynitride (a-SiOxNy) films. Since the PL properties and recombination processes are affected by both structural disorder and chemical disorder, the PL mechanism has been still unclear and even controversial until now. Among these various PL recombination models, the band tail states and defect states models have gained general consensus. Recently a N-Si-O bond defect model has been reported, which depends on relative atom concentration of oxygen and nitrogen in the silicon oxynitride materials. It has been revealed that oxygen bonding plays a key role not only in reducing the structural disorder, but also in creating N-Si-O (Nx) defect states in the band gap. The characteristics of two models, namely band tail and N-Si-O bond defects, have been discussed in detail. Finally it has been shown that by controlling the chemical composition of these non-stoichiometric silicon oxynitride materials, the optical and electronic properties can be improved.

Neuropixels Data-Acquisition System: A Scalable Platform for Parallel Recording of 10 000+ Electrophysiological Signals

Although CMOS fabrication has enabled a quick evolution in the design of high-density neural probes and neural-recording chips, the scaling and miniaturization of the complete data-acquisition systems has happened at a slower pace. This is mainly due to the complexity and the many requirements that change depending on the specific experimental settings. In essence, the fundamental challenge of a neural-recording system is getting the signals describing the largest possible set of neurons out of the brain and down to data storage for analysis. This requires a complete system optimization that considers the physical, electrical, thermal and signal-processing requirements, while accounting for available technology, manufacturing constraints and budget. Here we present a scalable and open-standards-based open-source data-acquisition system capable of recording from over 10,000 channels of raw neural data simultaneously. The components and their interfaces have been optimized to ensure robustness and minimum invasiveness in small-rodent electrophysiology.

All-silicon reconfigurable metasurfaces for multifunction and tunable performance at optical frequencies based on glide symmetry

Dielectric metasurfaces have opened promising possibilities to enable a versatile platform in the miniaturization of optical elements at visible and infrared frequencies. Due to high efficiency and compatibility with CMOS fabrication technology, silicon-based metasurfaces have a remarkable potential for a wide variety of optical devices. Adding tunability mechanisms to metasurfaces could be beneficial for their application in areas such as communications, imaging and sensing. In this paper, we propose an all-silicon reconfigurable metasurface based on the concept of glide symmetry. The reconfigurability is achieved by a phase modulation of the transmitted wave activated by a lateral displacement of the layers. The misalignment between the layers creates a new inner periodicity which leads to the formation of a metamolecule with a new sort of near-field interaction. The proposed approach is highly versatile for developing multifunctional and tunable metadevices at optical frequencies. As a proof of concept, in this paper, we design a bifunctional metadevice, as well as a tunable lens and a controllable beam deflector operating at 1.55 μm.

From Design to Tape-out in SCL 180 nm CMOS Integrated Circuit Fabrication Technology

ABSTRACTAlthough India has achieved considerable capability in electronic chip design, but developing the infrastructure for capital-intensive semiconductor fabrication remains a challenge. The rising domestic and global demand for electronics products, the need of enhancing the country’s high-technology talent pool, employment generation, and national security concerns dictates the Indian Government’s heightened efforts in promoting electronics hardware manufacturing in the country. A recent milestone in this regard is the setting up of 180 nm CMOS fabrication facility at SCL, Chandigarh. The Multi Project Wafer runs of this indigenous foundry promises to be a relatively cost-effective option for Indian academic and R&D institutions in realising their designed VLSI circuits. Written from the perspective of an Analog VLSI designer, this tutorial paper strives to provide all the requisite information and guidance that might be required in order to prepare chip designs for submission to SCL for fabrication.