ASIC Design of Low Power Sobel Edge Detection Filter: An Analog Approach

Abstract

This paper proposes a novel analog front end to filter edges in captured images. The proposed architecture employs the Sobel algorithm and uses a 3 ×3 kernel to process the input images. We used 180 nm Semi-Conductor Laboratory (SCL) CMOS fabrication technology for implementation with a power supply of 1.8 V. The proposed design employs six analog differential pairs in each horizontal and vertical gradient unit. The inputs to the differential pairs are the active signals fed from the 3 ×3 kernel using the Sobel weight masks. We connected the differential datum pairs in cascade to estimate the gradient index in horizontal/vertical direction using the net difference current between the output terminals. The horizontal and vertical gradient units, viz., [Formula: see text] and [Formula: see text], respectively, are configured based on the polarity of weights in respective Sobel masks. The gradient [Formula: see text] of the processing pixel (PP) is estimated using the net difference current in the combined circuitry employing [Formula: see text] and [Formula: see text] cells. The key advantages of the proposed design are very low area realization, high accuracy, and low power dissipation. The efficacy of the proposed edge filter analog front end is estimated through simulations and analysis with two sets of test signals in the processing window.