CMOS Design Rules Research Articles

Heterogeneously integrated impedance measuring system with disposable thin-film electrodes

We propose a novel integrated impedance measurement system with disposable thin-film electrodes. Most modern CMOS-based biosensors use on-chip electrodes to interface between the electronics and biosamples, which forces disposal of the CMOS chip after a few measurements, since most biological reactions are non-reversible. The sensor performance is also limited by the design of on-chip electrodes due to the physical dimensions and the CMOS design rules restrictions. In this work, we extract the electrodes from the silicon chip for relocation onto a low-cost, disposable substrate. This enables reusability of the high-performance CMOS chip, at the same time providing a low-cost route for manufacture of the active thin-film electrodes using large-area processing. The use of disposable thin-film chip also enables customised designed electrodes for different applications, such as extra high sensitivity concentration sensors. In this work, DNA concentration measurements are performed, and it shows a doubling of sensitivity over the previously reported system.

Analysis of single-event upset of magnetic tunnel junction used in spintronic circuits caused by radiation-induced current

This paper describes the possibility of a switching upset of a magnetic tunnel junction (MTJ) caused by a terrestrial radiation-induced single-event-upset (SEU) current in spintronic integrated circuits. The current waveforms were simulated by using a 3-D device simulator in a basic circuit including MTJs designed using 90-nm CMOS parameters and design rules. The waveforms have a 400 -μA peak and a 200-ps elapsed time when neutron particles with a linear energy transfer value of 14 MeV cm2/mg enter the silicon surface. The authors also found that the SEU current may cause soft errors with a probability of more than 10−12 per event, which was obtained by approximate solution of the ordinary differential equation of switching probability when the intrinsic critical current (IC0) became less than 30 μA.

Modeling the characteristics of trigger elements of two-phase CMOS logic, taking into account the charge sharing effect under exposure to single nuclear particles

The fault tolerance of CMOS D and RS flip-flops with a two-phase structure and memory cells based on them under exposure to single nuclear particles depends on the response to charge collection by several nodes. The relation between pairs of nodes with identical critical characteristics and specifics of symmetry of electric couplings between trigger transistors was established for DICE and Quatro cells. Critical pairs of nodes with minimal critical charges and an increased noise immunity were determined. The guidelines for mutual arrangement of transistors in DICE cells were given. The examples of quantitative estimation of critical dependences were given for cells with a 65 nm bulk CMOS design rule. DICE cells have an advantage in the event of multiple influence on the nodes.

Low-Power High-Speed Small Area Hybrid CMOS Full Adder

A 20-transistor hybrid CMOS full adder circuit using small area transistors has been proposed. The circuit layout is designed with 0.18-μm n-well CMOS design rules. The post layout simulation has been carried out using TSMC018 technology file. The proposed adder circuit provides fully restored logic levels at the output for all input combinations up to an operating frequency of more than 500 MHz. The power dissipation, rise and fall times, and worst-case propagation delay as obtained from the proposed adder have been found to be better in comparison to other full adder circuits (which provide fully restored logic levels at the output) reported in the literature.

Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture

This paper presents a novel architecture to increase the hardware utilization in multi-context field programmable gate arrays (MC-FPGAs). Conventional MC-FPGAs use dedicated tracks to transfer context-ID bits. As a result, hardware utilization ratio decreases, since it is very difficult to map different contexts, area efficiently. It also increases the context switching power, area and static power of the context-ID tracks. The proposed MC-FPGA uses the same wires to transfer both data and context-ID bits from cell to cell. As a result, programs can be mapped area efficiently by partitioning them into different contexts. An asynchronous multi-context logic block architecture to increase the processing speed of the multiple contexts is also proposed. The proposed MC-FPGA is fabricated using 6-metal 1-poly CMOS design rules. The data and context-ID transfer delays are measured to be 2.03ns and 2.26ns respectively. We achieved 30% processing time reduction for the SAD based correspondance search algorithm.

Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation

A fine-grain reconfigurable VLSI for various applications including arithmetic operations is developed. In the fine-grain architecture, it is important to define a cell function which leads to high utilization of a logic block and reduction of a switch block. From the point of view, a universal-literal-based multiple-valued cell suitable for bit-serial reconfigurable computation is proposed. A series-gating differential-pair circuit is effectively employed for implementing a full-adder circuit of Sum and a universal literal circuit. Therefore, a simple logic block can be constructed using the circuit technology. Moreover, interconnection complexity can be reduced by utilizing multiple-valued signaling, where superposition of serial data bits and a start signal which indicates heading of one-word is introduced. Differential-pair circuits are also effectively employed for current-output replication, which leads to high-speed signaling to adjacent cells The evaluation is done based on 90 nm CMOS design rule, and it is made clear that the area of the proposed cell can be reduced to 78% in comparison with that of the CMOS implementatiuon. Moreover, its area-time product becomes 92% while the delay time is increased by 18%.

CMOS Cascode Source-Drain Follower for Monolithically Integrated Biosensor Array

Source-drain follower has been designed and implemented for monolithically integrated biosensor array. The circuit acts as a voltage follower, in which a sensing transistor is operated at fixed gatesource and gate-drain voltages. It operates at 10nW power dissipation. The wide-swing cascode configurations are investigated in constant and non-constant biasing methods. The constant biased cascode source-drain follower has the merit of small cell size. The chip was fabricated using 1.2μm standard CMOS technology, and a wide range of operation between 1nW and 100μW was demonstrated. The accuracy of the voltage follower was 30mV using minimum sized transistors, due to the variation of threshold voltage. The error in the output except for the threshold voltage mismatch was less than 10mV. The temperature dependence of the output was 0.11mV/°C. To improve the input voltage range and accuracy, non-constant biased cascode source-drain follower is examined. The sensor cell is designed for 10mV accuracy and the cell size is 105.3μm×81.4μm in 1.2μm CMOS design rules. The sensor cell was fabricated and showed that the error in the output except for the threshold voltage mismatch was less than 2mV in a range of total current between 3nA and 10μA and in a temperature range between 30°C and 100°C.

A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer

We describe a sub 100-mW H.264 MP@L4.1 integerpel motion estimation processor core for low power video encoder. It supports macro block adaptive frame field (MBAFF) encoding and bidirectional prediction for a resolution of 1920×1080 pixels at 30fps. The proposed processor features a novel hierarchical algorithm, reconfigurable ring-connected systolic array architecture and segmentation-free, rectangle-access search window buffer. The hierarchical algorithm consists of a fine search and a coarse search. A complementary recursive cross search is newly introduced in the coarse search. The fine search is adaptively carried out, based on an image analysis result obtained by the coarse search. The proposed systolic array architecture minimizes the amount of transferred data, and lowers computation cycles for the coarse and fine searches. In addition, we propose a novel search window buffer SRAM that has instantaneous accessibility to a rectangular area with arbitrary location. The processor core has been designed with a 90nm CMOS design rule. Core size is 2.5×2.5mm2. One core supports one-reference-frame and dissipates 48mW at 1V. Two core configuration consumes 96mW for two-reference-frame search.

Low-Power Field-Programmable VLSI Using Multiple Supply Voltages

A low-power field-programmable VLSI (FPVLSI) is presented to overcome the problem of large power consumption in field-programmable gate arrays (FPGAs). To reduce power consumption in routing networks, the FPVLSI consists of cells that are based on a bit-serial pipeline architecture which reduces routing block complexity. Moreover, a level-converter-less multiple-supply-voltage scheme using dynamic circuits is proposed, where the cells in non-critical paths use a low supply voltage for low power under a speed constraint. The FPVLSI is evaluated based on a 0.18-μm CMOS design rule. The power consumption of the FPVLSI using multiple supply voltages is reduced to 17% or less compared to that of the static-circuit-based FPVLSI using multiple supply voltages.

Micromachined high-Q inductors in a 0.18-μm copper interconnect low-k dielectric CMOS process

On-chip spiral micromachined inductors fabricated in a 0.18-/spl mu/m digital CMOS process with 6-level copper interconnect and low-K dielectric are described. A post-CMOS maskless micromachining process compatible with the CMOS materials and design rules has been developed to create inductors suspended above the substrate with the inter-turn dielectric removed. Such inductors have higher quality factors as substrate losses are eliminated by silicon removal and increased self-resonant frequency due to reduction of inter-turn and substrate parasitic capacitances. Quality factors up to 12 were obtained for a 3.2-nH micromachined inductor at 7.5 GHz. Improvements of up to 180% in maximum quality factor, along with 40%-70% increase in self-resonant frequency were seen over conventional inductors. The effects of micromachining on inductor performance was modeled using a physics-based model with predictive capability. The model was verified by measurements at various stages of the post-CMOS processing. Micromachined inductor quality factor is limited by series resistance up to a predicted metal thickness of between 6-10 /spl mu/m.

Fabrication of mega-bit FeRAM with both stacked Pt/SBTN/Pt/IrOx/Ir capacitor and 0.25μm cmos design rule

Pt/SrBi2(Tai1-xNbx)2O9/Pt/IrOx/Ir capacitor was successfully fabricated up to metallization on poly silicon plug for Mega-bit FeRAM. The integration processes include CMP technique, buried TiN barrier structure and electrode technology for high thermal stability, low temperature process for SBTN film. The thickness of iridium layer was the most important factor in controlling the contact resistance of the poly silicon plug. Pt/IrOx thickness also affected the contact resistance. But the RTO treatment of the TiN barrier layer did not change the contact resistance. The best contact resistance of the plug was about 2kΩ/plug in the maximum process temperature of 750°C, 3min in oxygen ambient at the contact size of 0.30 Ωm in diameter. Hysteresis curves of the SBTN capacitor were obtained after metallization. The switching polarization was about 10μC/cm2, and capacitor size dependency of the polarization was not observed in the range of 0.30 μm2 ∼25 μm2

Clock-delayed domino for dynamic circuit design

Clock-delayed (CD) domino is a self-timed dynamic logic family developed to provide single-rail gates with inverting or noninverting outputs. CD domino is a complete logic family and is as easy to design with as static CMOS circuits from a logic design and synthesis perspective. Design tools developed for static CMOS are used as part of a methodology for automating the design of CD domino circuits. The methodology and CD domino's characteristics are demonstrated in the design of a 32-b carry look-ahead adder. The adder was fabricated with MOSIS's 0.8-/spl mu/m CMOS process with scalable CMOS design rules that allow a 1.0-/spl mu/m drawn gate length. Measurements of the adder show a worst case addition of 2.1 ns. The CD domino adder is 1.6/spl times/ faster than a dual-rail domino adder designed with the same cell library and technology.

Design of Stacked SRAM Celt using Dual Port

A stacked SRAM cell for high density memories has been designed using two level polysilicon technology. The inverted thin film transistor forms the load, using common gate electrode (first polysilicon) to the driver transistor. Cell area is reduced by elimination of the N well, parallel layout and smaller cell ratio. Second polysilicon layer forms the drain/source and channel region of the TFT. It also offers superior electrical characteristics. The dual ports have been provided in the SRAM cell using a modified six transistor cell design to provide uncontested and overlapped two-port read access to one cell and read/write access to another. CMOS design rules have been used and as an example MOSIS technology with 0.5 μm design features have been chosen for computation.

Design of a reconfigurable VLSI processor for robot control based on bit-serial architecture

In realization of intelligent robots with the capability of quick response to altering environments, it is necessary to reduce the operation delay time of the sensor input signal to the control output. In this article, dynamically reconfigurable multioperand multiplication-addition based on bit-serial operations on multiple inputs is proposed. As a consequence, not only the utilization of the full address provided in the computational section, but also those of the local memory, controller, and distribution lines inside the chip, can thoroughly be improved. The structure of the corresponding reconfigurable VLSI processor is also proposed. In reconfigurable VLSI processors, the overhead of data transfer between processing elements (PE) is remarkably decreased, resulting in the reduction of the product of the PE chip area and the multiplication-addition time (i.e., area–time product). Therefore, the overall computation capability of the processor is remarkably improved. For example, performance evaluation of the chip based on the 0.8-μm CMOS design rule showed that the delay time of multioperand multiplications-additions and the area–time product are reduced threefold, compared with those of reconfigurable VLSI processors based on bit-parallel architecture. © 1999 Scripta Technica, Syst Comp Jpn, 30(12): 43–51, 1999

Design of a reconfigurable VLSI processor for robot control based on bit‐serial architecture

In realization of intelligent robots with the capability of quick response to altering environments, it is necessary to reduce the operation delay time of the sensor input signal to the control output. In this article, dynamically reconfigurable multioperand multiplication-addition based on bit-serial operations on multiple inputs is proposed. As a consequence, not only the utilization of the full address provided in the computational section, but also those of the local memory, controller, and distribution lines inside the chip, can thoroughly be improved. The structure of the corresponding reconfigurable VLSI processor is also proposed. In reconfigurable VLSI processors, the overhead of data transfer between processing elements (PE) is remarkably decreased, resulting in the reduction of the product of the PE chip area and the multiplication-addition time (i.e., area–time product). Therefore, the overall computation capability of the processor is remarkably improved. For example, performance evaluation of the chip based on the 0.8-μm CMOS design rule showed that the delay time of multioperand multiplications-additions and the area–time product are reduced threefold, compared with those of reconfigurable VLSI processors based on bit-parallel architecture. © 1999 Scripta Technica, Syst Comp Jpn, 30(12): 43–51, 1999

A new RTD-FET logic family

We describe a new family of clocked logic gates based on the resonant-tunneling diode (RTD). Pairs of RTDs form storage latches, and these are connected by networks consisting of field-effect transistors (FETs), saturated resistors, and RTDs. The design, operation, and expected performance of both a shift register and a matched filter using this logic are discussed. Simulations show that the RTD circuits can achieve higher performance in terms of speed and power in many signal processing applications. Compared to circuits using III-V FETs alone, the RTD circuits are expected to run nearly twice as fast at the same power or at the same speed with reduced power. Compared to circuits using Lincoln Laboratory's fully depleted silicon-on-insulator CMOS, implementation using state-of-the-art RTDs should operate five times faster when both technologies follow the CMOS design rules.

A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip

A modular architecture for a DRAM-integrated, multimedia chip with a data transfer rate of 6 to 12 Gbyte/s is proposed. The architecture offers the design flexibility in terms of both DRAM capacity and the logic-memory interface for use in a wide variety of applications. A DRAM macro built from cascadable DRAM bank modules having a 256-kb memory capacity and 128-b I/Os provides flexibility and reconfigurability of DRAM capacity and a high data transfer rate with an area of 6.4 mm/sup 2//Mb. A data transfer circuit (called the "reconfigurable data I/O attachment"), which is attached to the I/O lines of the DRAM macro, provides a flexible logic-memory interface by changing the data-transfer routes between the DRAM macro and logic circuits in real time. A 6.4-Gbyte/s test chip (called the "media chip") for three-dimensional computer graphics was fabricated to test the proposed design methodology. It integrates an 8-Mb DRAM and four pixel processors on an 8.35/spl times/14.6-mm chip by using a 0.4-/spl mu/m CMOS design rule.

Reconfigurable parallel VLSI processor for dynamic control of intelligent robots

In the sensor feedback control of intelligent robots, the delay time must be reduced for a large number of multiply-additions. To reduce the delay time for multi-operand multiply additions, the architecture of the reconfigurable parallel processor is proposed. In each PE, a switch circuit (SC) is used to change the connection between multipliers and adders. By changing the switch elements in the SC using the very-long-instruction-word (VLIW) control method, the multiply-adders having desired numbers of multipliers can be reconfigured every clock cycle. Since the data transfer is performed by the direct connection between multipliers and adders, the overhead for data transfer is greatly reduced. In addition, the utilised ratio of the multipliers and the adders is increased. The chip evaluation based on 0.8 /spl mu/m CMOS design rule shows that the delay time for dynamic control of a seven-degrees-of-freedom (DOF) redundant robot manipulator becomes about 10 /spl mu/s which is about 7.7 times faster than that of a parallel-processor approach using conventional digital signal processors (DSPs).

Cache-processor coupling: a fast and wide on-chip data cache design

This paper presents a new data cache design, cache-processor coupling, which tightly binds an on-chip data cache with a microprocessor. Parallel architectures and high-speed circuit techniques are developed for speeding address handling process associated with accessing the data cache. The address handling time has been reduced by 51% by these architectures and circuit techniques. On the other hand, newly proposed instructions increase data cache bandwidth by eight times. Excessive power consumption due to the wide-bandwidth data transfer is carefully avoided by newly developed circuit techniques, which reduce dissipation power per bit to 1/26. Simulation study of the proposed architecture and circuit techniques yields a 1.8 ns delay each for address handling, cache access, and register access for a 16 kilobyte direct mapped cache with a 0.4 /spl mu/m CMOS design rule.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

再構成可能並列プロセッサと知能ロボット制御への応用

In the sensor feedback control of intelligent robots, the delay time must be reduced for a large number of arithmetic operations. In addition to many multiply-additions, the arithmetic operations such as absolute value calculation and maximum value selection are often used in the dynamic control of robot manipulators. To reduce the delay time for multi-operand arithmetic operations, the architecture of the reconfigurable parallel processor is proposed. In each processor element, a switch circuit is used to change the connection between the multipliers, adders and arithmetic units (AUs), so that the multi-operand AUs having desired numbers of operands can be reconfigured. Since the data transfer is accomplished by the direct connection between the multipliers, adders and AUs, the overhead for data transfer is reduced. The chip evaluation based on 0.8 [μm] CMOS design rule shows that the delay time for differential inverse kinematics computation and inverse dynamics computation of a six-degrees-of freedom manipulator become 1.7 [μsec] and 11.5 [μsec], respectively.