Design of Stacked SRAM Celt using Dual Port

Abstract

A stacked SRAM cell for high density memories has been designed using two level polysilicon technology. The inverted thin film transistor forms the load, using common gate electrode (first polysilicon) to the driver transistor. Cell area is reduced by elimination of the N well, parallel layout and smaller cell ratio. Second polysilicon layer forms the drain/source and channel region of the TFT. It also offers superior electrical characteristics. The dual ports have been provided in the SRAM cell using a modified six transistor cell design to provide uncontested and overlapped two-port read access to one cell and read/write access to another. CMOS design rules have been used and as an example MOSIS technology with 0.5 μm design features have been chosen for computation.