CMOS Design Rules Research Articles

Coordinate Transformation VLSI Processor for Redundant Manipulator Control

A computationally efficient algorithm called 'Subsequent-division algorithm' is presented to develop a special-purpose VLSI processor for differential inverse kinematics computation of redundant manipulators. Because the computation is performed in a feedback loop, not only throughput but also absolute delay time must be considered as performance factor An architecture of a reconfigurable parallel VLSI processor is proposed to improve the utilized ratio of the multipliers contained in processor elements (PEs). In each PE, switching hardware is used to change the connections between the multipliers and the adders, so that we can reconfigure the multiply-adders having desired numbers of multipliers. The chip evaluation based on Iμm CMOS design rule shows that the total delay time for a 12 degrees-of-freedom (DOF) redundant manipulator becomes about 13μsec which is about ninety times faster than that of a parallel processor approach using general-purpose microprocessors.

A single 1.5-V digital chip for a 10/sup 6/ synapse neural network

A digital-chip architecture for a 10(6)-synapse neural network is proposed. It runs on a 1.5-V dry cell to allow its use in portable equipment. An on-chip DRAM cell array stores synapse weights digitally to provide easy programmability and automatic refreshing. A pitch-matched interconnection and a combinational unit circuit for summing product allow a tight layout. A dynamic data transfer circuit and the 1.5-V operation of the entire chip reduce the power dissipation, but the parallel processing nonetheless provides high speed at the 1.5-V supply. Estimated power dissipation of 75 mW and a processing speed of 1.37 giga connections per second are predicted for the chip. The memory and the processing circuits can be integrated on a 15.4-mmx18.6-mm chip by using a 0.5-mum CMOS design rule. A scaled-down version of the chip that has an 8-kb DRAM cell array was fabricated, and its operation was confirmed.

Formal definitions of edge-based geometric design rules

A structured method for geometric design rule definitions is presented in terms of edge-based constraints. Using this approach, intralayer design rules such as width and spacing of single layers, and interlayer design rules such as clearance, margin, extension, and overlap of two different layers can be specified in terms of two high-level design rule macros only. The tedious and complicated task of specifying detailed design rules in the technology file is thereby eliminated and placed by a simple macro rule file giving a much better overview of the design rules. Efficient rule compilers have been developed to expand these macro descriptions of the design rules onto basic checks for Magic and for corner-based design rule checking. As an example, the MOSIS scalable CMOS design rule set can be described in terms of the two design rule macros only. More complicated design rules, such as conditional and conjunctive design rules, are also discussed. >

Tunable membership function circuit for fuzzy control systems using CMOS technology

The membership function circuit (MFC) is used in the input parts of analogue fuzzy hardware systems. The fuzzy hardware can execute singleton fuzzy control algorithms. In the letter a voltage-input current-output membership function circuit is proposed. The characteristic of this building block is tunable and is useful for current-mode analogue fuzzy hardware. The proposed circuit was designed by using 3.5μm CMOS design rules, and its operations have been confirmed using PSPICE simulations.

Proposed MOSFET-C continuous time biquadratic building blocks with high-order implementation

Abstract A novel family of MOSFET-C continuous-time biquadratic building blocks is proposed in this paper. The proposed family realizes all generic transfer functions such as lowpass, highpass, bandpass, band rejection, and allpass. It achieves a complete MOS non-linearity cancellation and does not require the use of fully balanced op.-amps. The proposed blocks enjoy low passband sensitivities. A Monte Carlo analysis was done to verify the sensitivity performance. An example of bandpass filter with comparative study is given. The maximum dynamic range is adjusted using SPICE. All the design steps are matched with the 3.5 μm CMOS design rules. Then the proposed biquads are implemented to realize a transmission zeros bandpass filter of twelfth order.

Design and VLSI implementation of mod-127 multiplier using cellular automaton-based data compression techniques

A new technique for the design and VLSI implementation of a mod-127 multiplier based on two-dimensional cellular automata (CA) is presented in this paper using two-micrometre CMOS design rules. This technique uses the data compression capabilities of CA, which arise due to the availability of symmetrical global states, to reduce the silicon area required for these modulo arithmetic units by about 90%. The reduction in silicon area is achieved by using two identical triangular CA, each comprising 15 cells and an overflow bit, which are subjected to specific initial and boundary conditions. Encoding and decoding is performed on-chip and the complexity of the latter is significantly reduced by observing only a few critical cells that provide the signature for ascertaining the states of the CA. The silicon area occupied by the chip is 2.4 × 2.2 mm2 and it can operate with a clock frequency of 25 MHz with calculations requiring between 1 and 126 clock cycles to perform. VLSI complexity of the new approach is also compared with that of conventional ones. The paper has demonstrated the flexibility of the CA array architecture, in terms of modularity and parallelism, which is particularly well suited to implementation using VLSI.

BLITZEN: A highly integrated massively parallel machine

The goal of the BLITZEN project is to construct a physically small, massively parallel, high-performance machine. This paper presents the architecture, organization, and feature set of a highly integrated SIMD array processing chip which has been custom designed and fabricated for this purpose at the Microelectronics Center of North Carolina. The chip has 128 processing elements (PEs), each with 1K bits of static RAM. Unique local control features include the ability to modify the global memory address with data local to each PE, and complementary operations based on a condition register. With a 16K PE system (only 128 custom chips are needed for this), operating at 20 MHz, data I/O can take place at 10,240 megabytes per second through a new method using a 4-bit bus for each set of 16 PEs. A 16K PE system can perform IEEE standard 32-bit floating-point multiplication at a rate greater than 450 megaflops. Fixed-point addition on 32-bit data exceeds the rate of three billion operations per second. Since the processors are bit-serial devices, performance rates improve with shorter word lengths. The BLITZEN chip is one of the first to incorporate over 1.1 million transistors on a single die. It was designed with 1.25-pm, two-level metal, CMOS design rules on an 11.0 by 11.7-mm die.

A pipelined associated memory implemented in VLSI

A memory system which rapidly chooses the stored item most closely matching a given input is fundamental to a number of recognition tasks. A memory architecture which performs this function is discussed. In addition, a measure of the quality of the selected (best matching) memory is generated. The architecture is capable of significant data throughput rates and is amenable to implementation using conventional digital VLSI fabrication process. These characteristics are demonstrated by a prototype device fabricated using the MOSIS 3- mu m CMOS design rules, which can compare more than two million 9-bit input works per second. Behavioral simulations demonstrate the applicability of the architecture to some basic recognition tasks.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The graph search machine (GSM): A VLSI architecture for connected speech recognition and other applications

A programmable VLSI architecture is described for efficiently computing a variety of kernel operations for speech recognition. These operations include dynamic programming for isolated and connected word recognition using both the template matching approach and the Hidden Markov Model (HMM) approach, the use of finite-state grammars (FSG) for connected word recognition, and metric computations for vector quantization and distance measurement. These are collectively referred to as graph search operations since a diagram consisting of arcs and nodes is commonly used to illustrate the HMM or FSG. As well as being able to efficiently compute a wide class of speech processing operations, the architecture is useful in other areas such as image processing. A chip design has been completed using 1.75-µm CMOS design rules and combines both custom and standard cell aproaches.

CMOS — The emerging VLSI technology

The recent evolution in CMOS as the emerging very-large-scale-integrated (VLSI) circuit technology is reviewed. Various CMOS technologies and their impact on circuit performance and reliability are discussed and compared in generic and special circuit applications. Key issues in CMOS scaling, such as hot-electron effects, buried-channel characteristics, latchup, and isolation requirements, are briefly described. State-of-the-art CMOS design rules are also addressed. Future trends of CMOS technology development in VLSI circuits are discussed.

SCAPE: a single-chip array processing element for signal and image processing

The SCAPE chip is a practical implementation of a VLSI associative string processor; integrating a string of 256 identical processing elements, each comprising 37 bits of content-addressable memory, a 1-bit adder and logic for communication with other processing elements. Packing 143K transistors on a 73 mm2 silicon die, with 2.5 μm p-well (two-layer metal) CMOS design rules, the SCAPE chip is packaged in a 68-pin chip carrier and, operating at 10 MHz, dissipates less than 900 mW. The paper describes the SCAPE chip architecture and floor plan in structural detail. Testability considerations, design verification and SCAPE software are discussed, and the results from recent performance simulation studies are also reported. The SCAPE chip is scheduled for fabrication, by Plessey (Caswell), in the second quarter of 1986.

SCAPE: a single-chip array processing element for signal and image processing

The SCAPE chip is a practical implementation of a VLSI associative string processor; integrating a string of 256 identical processing elements, each comprising 37 bits of content-addressable memory, a 1-bit adder and logic for communication with other processing elements. Packing 143K transistors on a 73 mm2 silicon die, with 2.5 μm p-well (two-layer metal) CMOS design rules, the SCAPE chip is packaged in a 68-pin chip carrier and, operating at 10 MHz, dissipates less than 900 mW. The paper describes the SCAPE chip architecture and floor plan in structural detail. Testability considerations, design verification and SCAPE software are discussed, and the results from recent performance simulation studies are also reported. The SCAPE chip is scheduled for fabrication, by Plessey (Caswell), in the second quarter of 1986.