The graph search machine (GSM): A VLSI architecture for connected speech recognition and other applications

Abstract

A programmable VLSI architecture is described for efficiently computing a variety of kernel operations for speech recognition. These operations include dynamic programming for isolated and connected word recognition using both the template matching approach and the Hidden Markov Model (HMM) approach, the use of finite-state grammars (FSG) for connected word recognition, and metric computations for vector quantization and distance measurement. These are collectively referred to as graph search operations since a diagram consisting of arcs and nodes is commonly used to illustrate the HMM or FSG. As well as being able to efficiently compute a wide class of speech processing operations, the architecture is useful in other areas such as image processing. A chip design has been completed using 1.75-µm CMOS design rules and combines both custom and standard cell aproaches.