Real time connected word recognition with finite state grammar on the graph search array processor

Abstract

A linear array processor has been designed and built whose elements consist of a programmable pattern-matching VLSI and a block of local memory. The processor element is called the graph search machine (GSM), and the array processor is called the graph search array (GSA). The array is implemented on PC-compatible plug-in cards, four elements to a card, and currently 16 cards are supported in a parallel arrangement. The instruction rate for the fully configured array is 2.5 GIPS (gigainstructions per second) typical, and 5.6 GIPS peak. The instruction set of the GSM and likewise the GSA is optimized for computing distances and making decisions. These are the two kernel operations of pattern recognition. The GSA was designed primarily for development of connected-word speech recognition applications. To this end, a connected-word recognizer incorporating a single-pass (real-time) finite-state grammar has been developed to run on the array. This implementation is called the single-pass finite-state grammar (SPFSG). >