CMOS Counterparts Research Articles

Characterization of various FinFET based 6T SRAM cell configurations in light of radiation effect

The microelectronics circuits used in the aerospace applications work in an extremely radiated environment, causing a large possibility of a single event upset (SEU). Static random access memory (SRAM) is the most susceptible of these circuits as it occupies a significant area of the recent System-on-Chip (SoC) and also frequently store important data. Therefore, retaining data integrity with regards to SEUs has become a primary requirement of SRAM bit-cell design. Use of FinFET devices in the SRAM cell can offer higher resistance against radiation compared to the CMOS counterparts. In this work, using TCAD simulations, we have analysed effect of SEU on three different FinFET based 6T bit-cell configurations, in which number of fins in the access and pull-down transistors are different. We have analysed the effect of SEU at an angle of 90° and 60°.

Performance Investigation of FinFET-Based MO-CCII and its Applications: Resistor-Less Multi-Function Bi-Quadratic Filter and Balanced Modulator

This paper presents an optimal design of a high-performance multi-output second-generation current conveyor (MO-CCII) based on 20[Formula: see text]nm Fin-Shaped Field Effect Transistor (FinFETs). Proposed MO-CCII has very low port X impedance and very high port Y impedance. The performance of the CCII has been thoroughly investigated in terms of DC, AC and transient characteristics of terminal voltages and branch currents and frequency response of port impedances. CCII shows the excellent high-frequency response of voltage as well as current transfer gains. The 3[Formula: see text]dB BW of voltage and current transfer gains are 11.2[Formula: see text]GHz and 11[Formula: see text]GHz, respectively. CCII provides excellent performance over its CMOS counterpart. Also, a resistor-less multi-function bi-quadratic filter is proposed. The filter depends on two CCIIs, a capacitor and does not require any resistors. It has three inputs and one output and realizes low-pass, high-pass and band-pass filters from a similar setup. FinFETs in the linear region are utilized as variable resistor to control filter properties. Nevertheless, the proposed filter has two floating capacitors which can be effortlessly realized in these days’ integrated circuit advancements. Also, a balanced modulator is proposed utilizing the proposed FinFET-based CCII and FinFET transistors only. Balanced modulator’s frequency of operation obtained is in GHz range.

Rail-to-Rail Timing Signals Generation Using InGaZnO TFTs For Flexible X-Ray Detector

This paper reports on-chip rail-to-rail timing signals generation thin-film circuits for the first time. These circuits, based on a-IGZO thin-film transistors (TFTs) with a simple staggered bottom gate structure, allow row and column selection of a sensor matrix embedded in a flexible radiation sensing system. They include on-chip clock generator (ring oscillator), column selector (shift register) and row-selector (a frequency divider and a shift register). They are realised with rail-to-rail logic gates with level-shifting ability that can perform inversion and NAND logic operations. These logic gates are capable of providing full output swing between supply rails, V DD and V SS , by introducing a single additional switch for each input in bootstrapping logic gates. These circuits were characterised under normal ambient atmosphere and show an improved performance compared to the conventional logic gates with diode connected load and pseudo CMOS counterparts. By using these high-performance logic gates, a complete rail-to-rail frequency divider is presented from measurements using D-Flip Flop. In order to realize a complete compact system, an on-chip ring oscillator (output clock frequency around 1 kHz) and a shift register are also presented from simulations, where these circuits show a power consumption of 1.5 mW and 0.82 mW at a supply voltage of 8 V, respectively. While the circuit concepts described here were designed for an X-ray sensing system, they can be readily expanded to other domains where flexible on-chip timing signal generation is required, such as, smart packaging, biomedical wearable devices and RFIDs.

Characterization of single-ended 9T SRAM cell

We present a circuit-level technique of designing a lower write-power along with variability-resistant 9-MOFTET static random-access memory cell. Our proposed bitcell exhibits lower write-power consumption owing to reduction of activity factor and breakup of feedback path between the cross-coupled inverters during write operation. It exhibits higher read static noise margin (by 3.09 ×) compared with standard 6T SRAM cell @ minimum-area. LP9T shows higher static margin for write operation (by 41%) compared with 8T (S6T) @ iso-area (minimum-area). These improvements are achieved due to breakup of feedback path during the process of writing a bit on to the storage node. The paper investigates in detail the influence of variation in process related parameters, environmental parameters such as supply voltage and temperature on most of the important design parameters of the bitcell and compares the obtained simulation results with conventional 6-MOSFET (6T) and 8-MOSFET (8T) bitcells. It demonstrates its invariableness by showing 1.5 × tighter disperse in read time variability with a cost of 1.41 × higher read time compared with S6T @ minimum-area. It also exhibits 39% narrower disperse in read time variability in comparison to 8T @ iso-area. It draws lower power (2.06 ×) from supply voltage while flipping of stored data during write mode compared with standard 8T SRAM cell @ iso-area. It also compares key design metrics of LP9T with those of few other 9T SRAM cells found in the literature. This work also realizes the proposed design using CNFET. The CNFET-based design outperforms its CMOS counterpart in all respect.

Energy-Efficient Convolutional Neural Network Based on Cellular Neural Network Using Beyond-CMOS Technologies

In this article, we perform a uniform benchmarking for the convolutional neural network (CoNN) based on the cellular neural network (CeNN) using a variety of beyond-CMOS technologies. Representative charge-based and spintronic device technologies are implemented to enable energy-efficient CeNN related computations. To alleviate the delay and energy overheads of the fully connected layer, a hybrid spintronic CeNN-based CoNN system is proposed. It is shown that low-power FETs and spintronic devices are promising candidates to implement energy-efficient CoNNs based on CeNNs. Specifically, more than $10\times $ improvement in energy-delay product (EDP) is demonstrated for the systems using spin diffusion-based devices and tunneling FETs compared to their conventional CMOS counterparts.

Power and delay optimization of domino Schmitt trigger configurations with enhanced hysteresis voltage

Intricacy and performance estimation of VLSI IC’s escalates as the device dimension goes minuscule, but the performance of IC’s has been improved exponentially over the years. Schmitt triggers are Bi-stable networks that have extensive application in the Field of communication and Signal processing. Dynamic logic and Domino CMOS logics in circuit design possess number of advantages to design essential logic units such as Schmitt triggers. On the other hand, Static CMOS counterparts are slower in operation and they consume more area along with short circuit power dissipation. In this work, the domino Schmitt trigger is architecturally modified to reduce power consumption and regulate hysteresis to have better noise margin. This paper presents two domino techniques based Schmitt Trigger topologies which gives low power operation and improved hysteresis width. A CMOS 22 nm library model is used for the design and results are investigated and validated.

FINFET operational amplifier with low offset noise and high immunity to electromagnetic interference

Most amplifiers are less immune to the electromagnetic interference (EMI) signal conducted at the input terminals. Operational amplifiers also suffer from EMI signals. Improvement in designs is required to remove the noises in the signal. The designs can be either circuit level or device level. This paper presents the design of an operational amplifier using Fin Field Effect Transistors (FinFETs). The Operational amplifier is designed to minimize the offset by including a low pass filter at the input differential pair of the FinFET based circuit. The measured offset voltage is reduced by about 75% in the proposed structure compared to a conventional one. The Operational amplifier power consumption is reduced when compared to the CMOS counterpart

On Basic Boolean Function Graphene Nanoribbon Conductance Mapping

In this paper, we augment a trapezoidal Quantum Point Contact topology with top gates to form a butterfly Graphene Nanoribbon (GNR) structure and demonstrate that by adjusting its topology, its conductance map can mirror basic Boolean functions, thus one can use such structures instead of transistors to build carbon-based gates and circuits. We first identify by means of Design Space Exploration specific GNR topologies for 2- and 3-input {AND, NAND, OR, NOR, XOR, XNOR} and demonstrate by means of the Non-Equilibrium Green Function - Landauer based simulations that butterfly GNR-based structures operating at $V_{\text {DD}}=$ 0.2 V outperform 7 nm @ $V_{\text {DD}}=$ 0.7 V CMOS counterparts by 2 to 3, 1 to 2, and 3 to 4, orders of magnitude in terms of delay, power consumption, and power-delay product, respectively, while requiring 2 orders of magnitude less active area. Subsequently, we investigate the effect of $V_{{\text {DD}}}$ variations and the $V_{{\text {DD}}}$ value lower bound. We demonstrate that the NOR butterfly GNR structures are quite robust as their conductance and delay are changing by no more than 2% and 6%, respectively, and that AND and NOR GNR geometries can operate even at 10 mV. Finally, we consider the aspects related to the practical realization of the proposed structures and conclude that even if there are still hurdles on the road ahead the latest graphene fabrication technology developments, e.g., surface-assisted synthesis, our proposal opens an alternative towards effective carbon-based nanoelectronic circuits and applications.

Leakage Current and Static Power Analysis of TFET 8T-SRAM Cell

Static Random Access Memory (SRAM) is primarily used for design of upper-level memories such as registers and caches due to its speed and reliability. The Gallium-Nitride (GaN) TFET[1] designed by Notre Dame University has a sub-threshold slope closer to 30mV/decade. It operates at 0.6V and has lower static leakage when compared to its’ CMOS counterparts. These properties make TFETs a favourable choice for the design of SRAM cells. This paper focuses on the design, verification and analysis of an 8-transistor (8T) SRAM by cell using the Notre Dame University’s 20nm GaN TFET device

Utilizing Graphene Nano-Ribbon Transistor in Data Converters: A Comparative Study

In recent years, efforts to perform more processing operation on a silicon chip have made a strong enthusiasm for making the circuit components smaller in order to reduce the power and increase the speed. Due to silicon constraints, there will be no possibility to follow Moore's law. That's why we should look for an alternative to silicon. Therefore, due to high mobility, high current density, and low noise, the study on Graphene Nano Ribbon (GNR) began. ADCs and DACs have a major share in the electronics industry. An ADC prepares signals for the digital world and microprocessor processing. There are different methods for converting analog to digital signals. Among them, due to unique features such as high speed; Flash ADC has attracted the attention of designers. In this research first, a model for simulating of the GNR field effect transistor (GNRFET), is introduced. Then, this model is used to design a flash ADC. The results of this study indicate that the designed circuit has a desirable performance as an ADC. In addition, compared to a same Si-CMOS sample, errors such as DNL, INL, Offset, and Full scale are reduced. Moreover, GNR-based ADC shows less power consumption. The maximum and minimum power consumption are equal to 27.8% and 17.6% which corresponds to 5-bit and 4-bit GNR-based flash ADCs compared with their CMOS counterpart. Moreover, this research indicates a significant improvement in the delay that is at least 86.3% and maximum 88.6% which corresponds to 5-bit and 3-bit GNR-based flash ADCs.

Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates

Reversible logic has 100% fault observability meaning that a fault in any circuit node propagates to the output stage. In other words, reversible circuits are latent-fault-free. Our motivation is to incorporate this unique feature of reversible logic to design CMOS circuits having perfect or 100% Concurrent Error Detection (CED) capability. For this purpose, we propose a new fault preservative reversible gate library called Even Target - Mixed Polarity Multiple Control Toffoli (ET-MPMCT). By using ET-MPMCT, we ensure that the evenness/oddness of applied 1’s at input, is preserved at all levels of a circuit including output level unless there is a faulty node. A single fault always destroys the parity of input at the output. Our design strategy has two steps for a given function: 1) implement the function with our proposed reversible ET-MPMCT gate library; and 2) apply reversible-to-CMOS gate conversion. For the first step, we propose two approaches. For our first approach in step 1, we first need to have a reversible form of the given function if it is irreversible. Then, synthesize the reversible function using Mixed Polarity Multiple Control Toffoli (MPMCT) gate library by conventional reversible logic synthesis techniques. Finally, the synthesized circuit is converted to ET-MPMCT constructed circuit which is fault preservative. Our second approach, is an ESOP - Exclusive Sum of Products - based synthesis approach modified for our proposed fault preservative ET-MPMCT gate library. It does work with both irreversible and reversible functions. We synthesize our circuits with both approaches in step 1 and choose the circuit with lower number of reversible gates to be fed to step 2 of our design strategy. In second step of our design strategy, we convert our fault preservative reversible circuits into their CMOS counterparts. The performance of our designs is compared with other CED schemes in the literature in terms of area, power consumption, delay and detection rate. Simulations are done with Cadence Genus tool using TSMC 40nm technology. Clearly, results are in favor of our proposed techniques.

Graphene Nanoribbon Based Complementary Logic Gates and Circuits

As CMOS feature size is reaching atomic dimensions, unjustifiable static power, reliability, and economic implications are exacerbating, thereby prompting for conducting research on new materials, devices, and/or computation paradigms. Within this context, graphene nanoribbons (GNRs), owing to graphene's excellent electronic properties, may serve as basic structures for carbon-based nanoelectronics. In this paper, we make use of the fact that GNR behavior can be modulated via top/back gate contacts to mimic a given functionality and combine complementary GNRs for constructing Boolean gates. We first introduce a generic gate structure composed of a pull-up GNR performing the gate Boolean function and a pull-down GNR performing its complement. Then, we seek GNR dimensions and gate topologies required for the design of 1-, 2-, and 3-input graphene-based Boolean gates, validate the proposed gates by means of SPICE simulation, which makes use of a non-equilibrium Green's function Landauer formalism based Verilog-A model to calculate GNR conductance, and evaluate their performance with respect to propagation delay, power consumption, and active area footprint. Simulation results indicate that, when compared with 7 nm FinFET CMOS counterparts, the proposed gates exhibit $\text{6}\times$ to 2 orders of magnitude smaller propagation delay, 2 to 3 orders of magnitude lower power consumption, and necessitate 2 orders of magnitude smaller active area footprint. We further present full adder (FA) and SRAM cell GNR designs, as they are currently fundamental components for the construction of any computation system. For an effective FA implementation, we introduce a 3-input MAJORITY gate, which apart of being able to directly compute FA's carry-out is an essential element in the implementation of error correcting codes codecs, which outperforms the CMOS equivalent carry-out calculation circuit by 2 and 3 orders of magnitude in terms of delay and power consumption, respectively, while requiring 2 orders of magnitude less area. The proposed FA exhibits $\text{6.2}\times$ smaller delay, 3 orders of magnitude less power consumption, while requiring 2 orders of magnitude less area, when compared with the 7 nm FinFET CMOS counterpart. However, because of the effective carry-out circuitry, a GNR-based $n$-bit ripple carry adder, whose performance is linear in the carry-out path, will be $\text{108}\times$ faster than an equivalent CMOS implementation. The GNR-based SRAM cell provides a slightly better resilience to dc-noise characteristics, while performance-wise has a $\text{3.6}\times$ smaller delay, consumes 2 orders of magnitude less power, and requires 1 order of magnitude less area than the CMOS equivalent. These results clearly indicate that the proposed GNR-based approach is opening a promising avenue toward future competitive carbon-based nanoelectronics.

Design of New Multi-Column 5,5:4 Compressor Circuit Based on Double-Gate UTBSOI Transistors

Abstract In the modern electronic devices, compressor circuits are used to speed up the partial product addition (PPA) stage in the multipliers. This paper presents an architecture of multi-column 5,5:4 compressor whose new transistor level implementation has been carried out through the ultra-thin-body silicon-on-insulator (UTBSOI) transistors. Such compressor has been simulated in Cadence-spectre, and the performance parameters like power consumption and delay has been calculated at the rising and falling edge transition of input pulses. Advantage of the UTBSOI-compressor is further clarified from its comparison with the CMOS based design (CMOS-compressor). Simulation results reveal that the PDP exhibited by the UTBSOI-compressor is reduced by 79.89% than that of CMOS counterparts. Furthermore, to showcase the advantage of such compressor, it has been applied in the multiplier for PPA which offers ≈11.5% improvement in terms of power-delay-product (PDP) in the Virtex 6 platform.

Efficient VLSI Implementation of a Sequential Finite Field Multiplier Using Reordered Normal Basis in Domino Logic

In this paper, a high-speed power-efficient VLSI implementation of a finite field multiplier in GF( $2^{m}$ ) is presented. The proposed design has a serial-in parallel-out architecture and performs the multiplication operation using a reordered normal basis. The basic idea is to implement the main building block of the multiplier in domino logic to reduce the critical path delay. Reduction in dynamic power consumption is achieved by limiting the contention current between the keeper transistor and the pull-down network at the beginning of the evaluation phase by employing a new keeper control circuit. The semicustom layout of the multiplier was realized in 65-nm CMOS technology. The post place-and-route simulations showed that the multiplier can perform multiplication correctly up to a clock rate of 3.85 GHz and consumes marginally less power than the static CMOS counterpart (also implemented with custom placement and route). The size of the multiplier is currently recommended by the National Institute of Standards and Technology for binary field multiplication in elliptic curve cryptography. The proposed design methodology can also be used in the implementation of similar finite field multipliers possessing regular architectures.

340 GHz lens‐coupled 4 × 4 GaAs detector array for terahertz imaging applications

A 340 GHz 4 × 4 detector array based on 0.18 µm gallium arsenide technology is presented. Each pixel is composed of a planar log-periodic antenna, a Schottky barrier diode, and a pair of bonding pads. The detector array is mounted on a silicon lens and assembled onto a PCB using the authors’ novel flip-chip structure. Off-axis performances of the lens-coupled detector array are demonstrated experimentally, which agree well with the simulated ones. The detector array shows a peak voltage responsivity of 1347 V/W and a noise equivalent power of 2.1 pW/Hz1/2 at 340 GHz, exhibiting much better performance than the CMOS counterpart.

Ultrahigh detection sensitivity exceeding 105 V/W in spin-torque diode

Microwave detection has a huge number of applications in physics and engineering. It has already been shown that biased spin torque diodes have performance overcoming the CMOS counterpart in terms of sensitivity. In this regard, the spin torque diodes are promising candidates for the next generation of microwave detectors. Here, we show that the optimization of the rectification process based on the injection locking mechanism gives an ultrahigh sensitivity exceeding 200 kV/W with an output resistance below 1 kΩ while maintaining the advantages over other mechanisms such as vortex expulsion or non-linear resonance, to work without a bias magnetic field.

Double-precision Dual Mode Logic carry-save multiplier

In this paper, a double-precision carry-save adder (CSA)-based array multiplier is designed using the Dual Mode Logic (DML) approach in a commercial 65-nm low-power CMOS technology. DML typically allows on-the-fly controllable switching at the gate level between static and dynamic operation modes. The proposed multiplier exploits this unique ability of DML to efficiently trade performance and energy consumption when considering on-demand double-precision (8 × 8-bit or 16 × 16-bit) operations. This occurs in the DML multiplier working in a mixed operation mode, i.e., by employing the static and dynamic mode for lower and higher precision operations, respectively. In fact, the use of the dynamic mode for higher precision operations ensures higher performance as compared to the standard CMOS circuit (16% gain on average) at the cost of higher energy consumption. Such energy penalty is counterbalanced at lower precision operations where the static mode is enabled in the DML circuit. Overall, the adoption of the mixed operation mode in the proposed DML multiplier proves to be beneficial to achieve a better performance/energy trade-off with respect to the standard CMOS implementation and to the case when using either the static or the dynamic mode for both operations at the two different precisions. When compared to its CMOS counterpart, our DML design operating in the mixed mode exhibits an average improvement of 15% in terms of energy-delay product (EDP) under wide-range supply voltage scaling. Such benefit is maintained over process-voltage-temperature (PVT) variations.

Log Domain Integrator using Quasi-Floating Gate MOSFET

Background: A MOS transistor operating in weak inversion exhibits logarithmic behavior and could serve as replacement of bipolar transistors which have often been employed in implementing log domain circuits. However, threshold voltage restricts the operation of MOS based log domain circuits at low supply voltage which could be eliminated by floating gate transistors (FGMOS) at the cost of low gain, low output impedance and degraded bandwidth. These limitations can be further overcome by using quasi-floating gate MOSFET (QFGMOS).The log domain technique has been employed to enhance the dynamic range of analog circuits suitable of operation at low supply voltage. Methods: In this paper, we have designed QFGMOS based integrator and its performance has been compared with CMOS and FGMOS versions. The behavior of these circuits has been verified by using OrCAD PSpice with level 7 parameters for 0.13 µm technology obtained from TSMC with supply voltage of 1V. Results: It has been observed that QFGMOS based compressor and expander exhibits better performance as compared to their CMOS and FGMOS counterparts. Further QFGMOS based log domain integrator has been designed and its performance compared with that of CMOS and FGMOS based log domain integrators and found that QFGMOS based log domain integrator exhibits larger bandwidth (4.26 MHz) as compared to FGMOS (3.2 MHz) and it dissipates less power (88.7 µW) then FGMOS (0.114 mW) and CMOS (0.129 mW) based log domain integrators and could be useful for low voltage applications. Conclusion: In this paper functional blocks of log domain integrator like compressor and expander have been designed using CMOS, FGMOS, QFGMOS transistors and their performance studied through PSpice simulations. It has been observed that QFGMOS based compressor and expander exhibits better performance as compared to their CMOS and FGMOS counterparts. Further QFGMOS based log domain integrator has been designed and its performance compared with that of CMOS and FGMOS based log domain integrators. Keywords: Compressor, expander, integrator, log domain, weak inversion, threshold voltage.

Analysis of Hybrid SETMOS T-Gate using Quaternary Multiple Valued (MV) Logic

In future nanometer technology, Single electron devices are promising device element to meet the demand for increasing in density, performance and power dissipation in ultra large scale integration. It appears that CMOS and SETs are rather complementary to each other; it is also true that combining SET and CMOS can provide a new functionality, which is un-mirrored in pure CMOS technology. SET with CMOS hybrid architecture is commonly referred to as SETMOS. It offer coulomb blockade oscillation and quasi periodic negative differential effect which gives an advantage to realize MV logic. Transmission (T)-gate act as universal gate which is implemented by using MV SETMOS. In this paper T-gate is proposed using literal gate of SETMOS device and its application such as single and two variables (multiple) function which act as basic blocks of sequential, logical circuits. Herein, the design functionality of quaternary multiple-valued logic is implemented by using voltage mode SETMOS. Analytical MIB model for SET is calibrated with BSIM 4.6.1 bulk MOSFET at 45 nm. The simulated waveform of circuits is carried out at room temperature in T-spice pro-environment. The proposed circuit with SETMOS device consumes merely 2050 nw of power along with 81 ps delay in comparison to its CMOS counterparts. Several intrinsic parameters (such as propagation delay, switching energy, area and voltage gain) play crucial role in determining the efficiency of the proposed quaternary MV logic T-gate is also investigated.

Low-Leakage 3D Stacked Hybrid NEMFET-CMOS Dual Port Memory

The 3D stacked hybrid memory relies on a hysteretic Nano-Electro-Mechanical Field Effect Transistor (NEMFET) inverter to store data, and on adjacent CMOS based logic to allow for read/write operations, and data preservation. In this paper we assess the feasibility of a hybrid memory cell, and explore the design space of 3D stacked hybrid dual-port memory arrays which combine the appealing NEMFET properties, i.e., ultra-low leakage currents and abrupt switching, with the CMOS technology versatility. In the evaluation we performed a comparison in terms of footprint, access time, and energy, against state of the art CMOS dual-ports memories, considering small and large size memory arrays ( $8$ -Kbytes up to $128$ -Kbytes) implemented in various technology nodes. The 3D NEMFET-CMOS hybrid dual-port memory is on the average $25$ percent smaller and $8$ and $95$ percent larger in terms of footprint when compared to $90$ , and $45$ nm CMOS implementations, respectively. The write access time is approximately $2\times$ higher, as it is dominated by the mechanical movement of the NEMFET's suspended gate, while the read access time is about $12$ percent lower, when compared with $45$ nm CMOS counterparts. For small size memories our proposal results in at least $15$ percent and $23$ percent energy reductions for $100$ and $50$ percent data transition probability, respectively. For large size memories an energy reduction of about $40$ percent was obtained, as in this case the static energy is predominant.