Power and delay optimization of domino Schmitt trigger configurations with enhanced hysteresis voltage

Abstract

Intricacy and performance estimation of VLSI IC’s escalates as the device dimension goes minuscule, but the performance of IC’s has been improved exponentially over the years. Schmitt triggers are Bi-stable networks that have extensive application in the Field of communication and Signal processing. Dynamic logic and Domino CMOS logics in circuit design possess number of advantages to design essential logic units such as Schmitt triggers. On the other hand, Static CMOS counterparts are slower in operation and they consume more area along with short circuit power dissipation. In this work, the domino Schmitt trigger is architecturally modified to reduce power consumption and regulate hysteresis to have better noise margin. This paper presents two domino techniques based Schmitt Trigger topologies which gives low power operation and improved hysteresis width. A CMOS 22 nm library model is used for the design and results are investigated and validated.