CMOS Counterparts Research Articles

Ultra-low-leakage chip multiprocessor design with hybrid FinFET logic styles

FinFET has begun replacing CMOS at the 22nm technology node because of its enhanced ability to mitigate short-channel effects. Although leakage power of FinFET logic gates is lower than their CMOS counterparts, it still contributes to a large part of total power consumption. In this article, we show how ultra-low-leakage FinFET chip multiprocessors (CMPs) can be designed using a hybrid logic style. This hybrid style exploits the ultra-low-leakage feature of asymmetric-workfunction shorted-gate (ASG) FinFETs and the high-performance feature of shorted-gate (SG) FinFETs. We explore the impact of the hybrid style at both the module and CMP levels. To do this, we have developed FinFET logic libraries targeted at SG and ASG logic gates, suitably characterized for various parameters of interest. We have also modified existing tools and created a framework to evaluate the hybrid designs of SRAMs, caches, and CMPs. Using the design with SG FinFETs as the baseline for comparison, our experimental results show that the hybrid style can reduce leakage power of execution units to as low as 10.6% of the baseline without hurting performance, that of SRAMs to between 21.5% and 4.8% of the baseline with 0%-8.3% delay overhead, and that of CMPs to 10.0% of the baseline with negligible performance degradation.

Subthreshold Dual Mode Logic

In this brief, we introduce a novel low-power dual mode logic (DML) family, designed to operate in the subthreshold region. The proposed logic family can be switched between static and dynamic modes of operation according to system requirements. In static mode, the DML gates feature very low-power dissipation with moderate performance, while in dynamic mode they achieve higher performance, albeit with increased power dissipation. This is achieved with a simple and intuitive design concept. SPICE and Monte Carlo simulations compare performance, power dissipation, and robustness of the proposed DML gates to their CMOS and domino counterparts in the 80-nm process. Measurements of an 80-nm test chip are presented in order to prove the proposed concept.

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits

The quest for technologies with superior device characteristics has showcased Carbon-Nanotube Field-Effect Transistors (CNFET) into limelight. In this work we present physical design techniques to improve the yield of CNFET circuits in the presence of Carbon Nanotube (CNT) imperfections. Various layout schemes are studied for enhancing the yield of CNFET standard cell library. With the help of existing ASIC design flow, we perform system-level benchmarking of CNFET circuits and compare them to CMOS circuits at various technology nodes. With CNFET technology, we observe maximum performance gains for circuits with gate-dominated delays. Averaged across various benchmarks at 16 nm, we report 8× improvement in Energy-Delay-Product (EDP) with CNFET circuits when compared to CMOS counterpart. We also study the performance of a complete OpenRISC processor, where we see 1.5× improvement in EDP over CMOS at 16 nm technology node. Voltage scaling enabled by CNFETs can be explored in the future for further performance benefits.

Ultra Low Power, High Performance Negative Edge Triggered ECRL Energy Recovery Sequential Elements with Power Clock Gating

Flip flops form an indispensable building block in the design of digital systems. In this study, adiabatic switching technique is used in the design of low-power negative edge triggered energy recovery flip-flops. In particular, the negative edge triggered D, SR and JK flip-flop designs based on the Quasi-adiabatic ECRL (Efficient Charge Recovery Logic) architecture are proposed. The projected design is illustrated with an 8 bit Serial Input and Parallel Output shift register (SIPO). The setup time and hold time are minimal in negative edge triggering compared to the pulsed and positive edge triggering which contributes to the high performance and the signal integrity of the design. Additionally, glitching is avoided due to the edge triggering which in turn reduces the soft error rate in the flip-flops. The simulation results have shown improvements in power efficiency by 95 and 75%, respectively for the D flip-flop and 8 bit shift registers than their CMOS counter parts. Due to its several merits, this design can find many real time applications such as digital communication (cryptography), memories and shift registers in microcontrollers. The four phase power clocks are utilized in the pipelining of the stages of the shift register, which mitigates all the relevant timing problems addressed in the literature of flip flops. For simulation, SPICE EDA simulation environment using the 350 nm process technology library from Austria micro systems have been used.

A Novel High Performance Low Power Universal Gate Implementation in Subthreshold Region

any integrated circuit power consumption plays a paramount role and is considered as one of the top challenges in International technology roadmap for semiconductors. In this paper, a low power circuit designed to operate in subthreshold region is proposed. Voltage scaling technique is incorporated to reduce dynamic power consumption while static or leakage power is greatly reduced with forced stack technique. The present technique (VS-STACK) features very low power dissipation as compared to its standard CMOS counterparts in subthreshold region. The power consumption is curtailed by 20% to 90% together with a better power delay product (PDP) over a supply voltage range. The technique is tested on a 2-input NOR gate in the 45nm process. Tanner Tool EDA 13.0v is used for simulation.

PERFORMANCE EVALUTION OF CNTFET-BASED SRAM CELL DESIGN

Carbon Nanotube Field-Effect Transistor (CNTFET) technology with their excellent current capabilities, ballistic transport operation and superior thermal conductivities has proved to be a very promising and superior alternative to the conventional CMOS technology. A detailed analysis and simulation based assessment of circuit performance of this technology is presented here. As figures of merit speed, power consumption and stability are considered to evaluate the performance parameters of CNTFET-Based SRAM Cells with different chiral vectors for the optimum performance. A novel performance metric, presented as “SPR,” is used to assess these figures of merit. This comprehensive metric includes a metric of low power delay product (PDP) for write operation and high stability in the operation of a memory cell. It is shown that an 8T SRAM cell provides 73% higher SPR than Dual-Chiral based 6T SRAM cell for CNT technology and 124% higher SPR than its CMOS counterpart, thus attaining superior performance. The CNTFET-based 8T SRAM cell demonstrates that it provides high stability, low delay and low power, which is better than CNTFET-based 6T SRAM cell as well as CMOS SRAM cell.

Design of CNTFET-based 2-bit ternary ALU for nanoelectronics

This article presents a hardware-efficient design of 2-bit ternary arithmetic logic unit (ALU) using carbon nanotube field-effect transistors (CNTFETs) for nanoelectronics. The proposed structure introduces a ternary adder–subtractor functional module to optimise ALU architecture. The full adder–subtractor (FAS) cell uses nearly 72% less transistors than conventional architecture, which contains separate ternary cells for addition as well as subtraction. The presented ALU also minimises ternary function expressions with utilisation of binary gates for optimisation at the circuit level, thus attaining a simple design. Hspice simulations results demonstrate that the ALU ternary circuits achieve great improvement in terms of power delay product with respect to their CMOS counterpart at 32 nm.

Low voltage dual mode logic: Model analysis and parameter extraction

The Dual Model Logic (DML) family, which was recently introduced by our group for sub-threshold operation, provides an alternative design methodology to the existing low power digital design techniques. DML gates allow switching between static and dynamic modes of operation on-the-fly according to system requirements, presenting better tradeoff between Energy consumption and performance. In static mode, low voltage DML gates achieve very low Energy consumption with moderate performance, while in dynamic mode they achieve high performance, albeit with higher Energy consumption. In this paper we analyze DML gates operation in the sub- and near-threshold regions by employing a recently proposed transregional model for low supply voltages. The sizing methodology of low voltage DML is discussed and classical Logical Effort parameters are calculated for the 40nm DML basic gates. The design example of a DML full adder, implemented in a 40nm low power standard CMOS technology, is shown to compare the proposed method with its CMOS and Domino counterparts. Monte Carlo simulations are shown to demonstrate the DML immunity to process variations.

Subthreshold Dual Mode Logic

In this brief, we introduce a novel low-power dual mode logic (DML) family, designed to operate in the subthreshold region. The proposed logic family can be switched between static and dynamic modes of operation according to system requirements. In static mode, the DML gates feature very low-power dissipation with moderate performance, while in dynamic mode they achieve higher performance, albeit with increased power dissipation. This is achieved with a simple and intuitive design concept. SPICE and Monte Carlo simulations compare performance, power dissipation, and robustness of the proposed DML gates to their CMOS and domino counterparts in the 80-nm process. Measurements of an 80-nm test chip are presented in order to prove the proposed concept.

High-Speed Low-Power MCML Nanometer Circuits with Near-Threshold Computing

In this paper, the standard cells of the high-speed low-power MCML circuits with near-threshold computing are developed. The basic MCML standard cells include buffer/inverter, AND/NAND, XOR/XNOR, multiplexer, and full adder. The layout, abstract design and standard-cell characters of near-threshold MCML basic cells are described at a NCSU FreePDK 45nm technology. The 2-bit multiplier is verified by using the MCML cells. For normal supply voltage, the MCML basic gates can save more energy and have better performance than the traditional CMOS counterparts at 1GHz or higher operation frequencies. Near-threshold computing for MCML circuits is investigated by scaling down the supply voltage. The results show that the power consumption of MCML circuits that operate on near-threshold regions can be reduced without performance degrading.

Are QCA cryptographic circuits resistant to power analysis attack?

Quantum-dot cellular automata (QCA) technology is expected to offer fast computation performance, high density, and low power consumption. Thus, researchers believe that QCA may be an attractive alternative to CMOS for future digital designs. Side channel attacks, such as power analysis attacks, have become a significant threat to the security of CMOS cryptographic circuits. A power analysis attack can reveal the secret key from measurements of the power consumption during the encryption and decryption process. As there is no electric current flow in QCA technology, the power consumption of QCA circuits is extremely low when compared to their CMOS counterparts. Therefore, in this paper an investigation into both the best and worst case scenarios for attackers is carried out to ascertain if QCA circuits are immune to power analysis attack. A QCA design of a submodule of the Serpent cipher is proposed. In comparison to a previous design, the proposed design is more efficient in terms of complexity, area, and latency. By using an upper bound power model, the first power analysis attack of a QCA cryptographic circuit is presented. The simulation results show that even though the power consumption is low, it can still be correlated with the correct key guess, and all possible subkeys applied to the Serpent submodule can be revealed in the best case scenario. Therefore, in theory QCA cryptographic circuits would be vulnerable to power analysis attack. However, the security of practical QCA devices can be greatly improved by applying a smoother clock. Moreover, in the worst case scenario, the design of logically reversible QCA circuits with Bennett clocking could be used as a natural countermeasure to power analysis attack. Therefore, it is believed that QCA could be a niche technology in the future for the implementation of security architectures resistant to power analysis attack.

Optimized Design of a 32-nm CNFET-Based Low-Power Ultrawideband CCII

CMOS technology faces significant challenges like tunneling effect, random dopant fluctuation, and line edge roughness at channel lengths below 45 nm. Carbon nanotube-based electronics seems to be a better prospect for extending the saturating Moore's law because of its higher mobility, scalability, and better channel electrostatics. This paper presents an optimum design of a wide bandwidth, high-performance carbon nanotube field-effect transistor (CNFET) realization of a dual-output second-generation current conveyor (CCII±) at a 32-nm technology node. The performance of the CCII module has been thoroughly investigated in terms of number of carbon nanotubes (CNTs), the diameter of CNT and inter-CNT pitch. The parameters of individual CNFET are then modified to further improve the performance. The performance of the optimum CNFET (ITOPT)-based CCII is then compared with CMOS at different supply voltages. It has been found that CNFET-based CCII provides excellent high-frequency response and also consumes lower power at scaled supply voltage compared with its CMOS counterpart.

Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic

This paper presents a 14-tap 8-bit finite impulse response (FIR) test-chip that has been designed using a novel charge-recovery logic family, called Enhanced Boost Logic (EBL), to achieve high-speed and low-power operation. Compared to previous charge-recovery circuitry, EBL achieves increased gate overdrive, resulting in low latency overhead over static CMOS design. The EBL-based FIR has been designed with only 1.5 cycles of additional latency over its static CMOS counterpart, while consuming 21% less energy per cycle, based on post-layout simulations of the two designs. The test-chip has been fabricated in a 0.13 μ m CMOS process with a fully-integrated 3 nH inductor. Correct function has been validated in the 365-600 MHz range. At its resonant frequency of 466 MHz, the test-chip dissipates 39.1 mW with a 93.6 nW/MHz/Tap/InBit/CoeffBit figure of merit, recovering 45% of the energy supplied to it every cycle.

A 3‐dB Quadrature WLP Coupler for 60 GHz Applications

ABSTRACTA 60 GHz tandem coupler using offset broadside coupled lines is proposed in a WLP (Wafer Level Packaging) technology. The fabricated coupler has a core chip area of 750 μm × 385 μm (0.288 mm2). The measured results show an insertion loss of 0.44 dB, an amplitude imbalance of 0.03 dB and a phase difference of 87.6° at 60 GHz. Also the measurement shows an insertion loss of less than 0.67 dB, an amplitude imbalance of less than 0.31 dB, a phase error of less than 3.7°, an isolation of more than 29.7 dB and a return loss of more than 27.9 dB at the input ant coupled ports and more than 14.3 dB at the direct and isolated ports over the frequency band of 57-66 GHz, covering 60 GHz band both in Japan and US. To the best of our knowledge the proposed coupler achieves the lowest ever reported insertion loss and amplitude imbalance for a 3-dB coupler on a silicon substrate. With its superior performance and lower cost compared to the CMOS counterparts, the proposed coupler is a suitable candidate for low-cost high-performance millimeter-wave systems.

Comparative Study on Energy-Efficiencies of Single-Electron Transistor-Based Binary Full Adders Including Nonideal Effects

Performances and energy efficiencies of various single-electron transistor-based (SET-based) binary full adders (FAs) are comparatively investigated with optimization of device parameters by means of simulation program with integrated circuit emphasis models including nonideal effects commonly observed in really implemented SETs. The proposed binary decision diagram (BDD) cell-based 1-bit FA is the most promising in terms of energy efficiency (τ=0.3 aJ/state), power dissipation (P = 1.2 nW), delay (τ=20 ps), and immunity to process variations (background charge noise ΔQ0 <; ±0.112q and control gate capacitance mismatch ΔCcg <; 0.5 × Ccg) at the expense of hardware burden, compared with majority gate-based SET FAs (3.988 aJ/state, P = 15.95nW, τ=52 ps, ΔQ0 <; ±0.0392q, ΔCcg <; 0.35 × Ccg) and SET threshold logic gate-based FAs (3.845 aJ/state, P=15.38nW, τ=107 ps, ΔQ0 <; ±0.028q, ΔCcg <; 0.2 × Ccg). It is also found that the SET itself dominates the power dissipation in SET-based FAs and the static dc power plays a significant role in power consumption in SET-based FAs, compared with the dynamic power, regardless of the FA type. In addition, SET-based BDD FAs are compared with their CMOS counterparts.

All nMOS 10-T AQRC for Monolithic Chlorophyll Fluorescence SPAD Sensor

Development of monolithic all nMOS Automatic Quenching and Reset Circuit (AQRC) for chlorophyll fluorescence SPAD sensor is reported using Microwind 3.1 and LTSpice version IV for 120 nm technology. An efficient bio-signal acquisition with single-photon counting facility, fast quenching, and reset is described using only ten nMOS transistors. The uniqueness of the design ensures a minimum dead time of 1 nS between adjacent incident photons. This corresponds to a maximum attainable count rate of 1000 MCounts/sec, not previously reported. The power dissipation is low (20-mW standby), making the circuit an ideal candidate for portable instruments. This is the first of its kind complete monolithic nMOS AQRC reported ever with better features than its CMOS counterparts.

Design and Manufacture of Energy-Recycling Pads for Low-Power Chips

Energy-recycling output pad cells for driving adiabatic chips are designed, which have been fabricated with Chartered 0.35um process and tested. The proposed energy-recycling output pad cells include mainly bonding pads, electrostatic discharge (ESD) protection circuits, and two stage energy-recycling buffers that are used to drive the large load capacitances on chip pads. The two stage energy-recycling buffers are realized using CPAL (Complementary Pass-transistor Adiabatic Logic) and PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration), respectively. For comparison, a conventional output pad cell is also embedded in the test chip. The function verifications and energy loss tests for the three output pad cells are carried out. The energy consumption of the proposed two energy-recycling output pad cells has large savings over a wide range of frequencies, as compared with the conventional CMOS counterparts, since the energy on large load capacitances in the chip pads can be well recycled.

True Energy-Performance Analysis of the MTJ-Based Logic-in-Memory Architecture (1-Bit Full Adder)

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> The use of spin-transfer torque (STT) devices for memory design has been a subject of research since the discovery of the STT on MgO-based magnetic tunnel junctions (MTJs). Recently, MTJ-based computing architectures such as logic-in-memory have been proposed and claim superior energy-delay performance over static CMOS. In this paper, we conduct exhaustive energy-performance analysis of an STT-MTJ-based logic-in-memory (LIM-MTJ) 1-bit full adder and compare it with its corresponding CMOS counterpart. Our results show that the LIM-MTJ circuit has no advantage in energy-performance over its equivalent CMOS designs. We also show that the MTJ-based logic circuit requiring frequent MTJ switching during the operation is hardly power efficient. </para>

Design of a CNTFET-Based SRAM Cell by Dual-Chirality Selection

This paper proposes a new design of a highly stable and low-power static RAM (SRAM) cell using carbon nanotube FETs (CNTFETs) that utilizes different threshold voltages for best performance. In a CNT, the threshold voltage can be adjusted by controlling the chirality vector (i.e., the diameter). In the proposed six-transistor SRAM cell design, while all CNTFETs of the same type have the same chirality, n-type and p-type transistors have different chiralities, i.e., a dual-diameter design of SRAM cell. As figures of merit, stability, power dissipation, and write time are considered when selecting the chirality for the best overall performance. A new metric, denoted as ¿SPR,¿ is proposed to capture these figures of merit. This metric shows that a CNTFET-based SRAM cell provides an ¿SPR¿ that is four times higher than for its CMOS counterpart that has the same configuration, thus attaining superior performance. Finally, the sensitivity of the CNTFET SRAM design to process variations is assessed and compared with its CMOS design counterpart. Extensive simulations have been performed to investigate the distribution of the power and delay of the CNTFET-based SRAM cell due to variations in the diameter, supply voltage, and temperature of the CNTFETs. The CNTFET-based SRAM cell demonstrates that it tolerates the process, power supply voltage, and temperature variations significantly better than its CMOS counterpart.

Leakage Current Reduction Using Subthreshold Source-Coupled Logic

The performance of subthreshold source-coupled logic (STSCL) circuits for ultra-low-power applications is explored. It is shown that the power consumption of STSCL circuits can be reduced well below the subthreshold leakage current of static CMOS circuits. STSCL circuits exhibit a better power-delay performance compared with their static CMOS counterparts in situations where the leakage current constitutes a significant part of the power dissipation of static CMOS gates. The superior control on power consumption, in addition to the lower sensitivity to the process and supply voltage variations, makes the STSCL topology very suitable for implementing ultra-low-power low-frequency digital systems in modern nanometer-scale technologies. An analytical approach for comparing the power-delay performance of these two topologies is proposed.