CMOS Comparator Research Articles

An Auto Offset Calibration Method for High-resolution Continuous CMOS Comparators

An Auto Offset Calibration Method for High-resolution Continuous CMOS Comparators

An Review of Dynamic CMOS Comparators

CMOS dynamic comparators contributes a major role on the implementation of mixed signal successive approximation register (SAR) type of analog to digital converters (ADC). High precision, dynamic range, low voltage operation, high speed, low power consumption, reliability and offset voltage are the critical factors to be considered while designing CMOS dynamic comparators. This paper reviewed the performance of some popular dynamic CMOS comparators such as StrongARM latch comparator, double- tail dynamic-latched comparator, dynamic bias comparator and triple stage somparator.

Fast and Low-Power CMOS and CNFET based Hysteresis Voltage Comparator

This paper presents CMOS and CNFET based hysteresis voltage comparators for low-voltage applications. The proposed CMOS and CNFET hysteresis comparators require merely 1.6 and 0.26 µW of power, respectively, which is less than one tenth of the power dissipated by the other advanced hysteresis comparators designs available in literature. The propagation delay observed in the proposed CMOS and CNFET hysteresis comparators are 162 and 47 ps, respectively, which is almost half the delay exhibited by the other hysteresis comparators. Overall, a 93–99% reduction in Power Delay Product (PDP) can be achieved. Furthermore, the proposed design requires only nine transistors compared to the 11–17 transistor requirement in conventional hysteresis comparators, thus saving up to 47% of chip area.

Design Of Three Stage Comparator Using 90nm Technology

In this paper, the design of three stage comparator using 90nm technology is presented. The comparator is one of the block that limits the speed of the converter, its optimization is crucial and important and design of Analog-to-Digital Converter (ADC),is the speed limiting element in comparator. It describes the schematic design of a three stage CMOS comparator to achieve lower power dissipation and a lower offset voltage, with high-speed operation. Test structure of the comparator are designed using GPDK 90nm. The three-stage comparator makes it possible to use NMOS input pairs in both the regeneration stage and the amplification stage, further increasing the speed. Furthermore, in the modified version of three-stage comparator, a CMOS input pair is adopted at the amplification stage. Simulation results are obtained and it shows that the proposed design can work under 1.8V supply, with an offset voltage of 200mV, and thus, an innovative circuit technique is implemented to overcome these limitations. The work carried out is the mini-project that is a part & parcel of the curriculum in the 2nd semester.

Implementation of 32-BIT Pipelined ADC Using 90nm Analog CMOS Technology

After seeing the technological evolution, we have understood about the A/D converter that it is the meeting point of the analog to digital domains. As technology is being continuously scaled down, the transistor sizes have decreased drastically resulting in reduced area and power consumption in the digital domain. The successive approximation ADC is best suitable for low power applications with moderate speed and simple design. Here, the implementation of 32-bit pipelined analog-to-digital converter with the help of successive approximation register based Sub-ADC. The SAR ADC architectures are popular for achieving high energy efficiency and low power applications. But they suffer from resolution and speed limitation. To overcome the speed limitations of SAR ADC, we proposed the implementation of 90nm using CMOS technology of a low power, high speed pipelined analog-to-digital converter (ADC). The capacitive digital-to-analog converter (DAC), two stage CMOS comparator with output inverter of proposed ADC are lower than those of a conventional ADC. To achieve low power and to minimize the size of the input sampling capacitance in order to ease durability.

Recursive Threshold Logic-A Bioinspired Reconfigurable Dynamic Logic System With Crossbar Arrays.

The neuron behavioral models are inspired by the principle of the firing of neurons, and weighted accumulation of charge for a given set of input stimuli. Biological neurons show dynamic behavior through its feedback and feedforward time-dependent responses. The principle of the firing of neurons inspires threshold logic design by applying threshold functions on the weight summation of inputs. In this article, we present a recursive threshold logic unit that uses the output feedback from standard threshold logic gates to emulate Boolean expressions in a time-sequenced manner. The Boolean expression is implemented with an analog resistive divider in memristive crossbars and a hard-threshold function designed with CMOS comparator for realizing the sums (OR) and products (AND) operators. The method benefits from reliable programming of the memristors in 1T1R crossbar configuration to suppress sneak path currents and thus enable larger crossbar sizes, which in turn allow a higher number of Boolean inputs. The reference threshold voltage for the decision comparators is tuned to implement AND and OR logic. The threshold value range is limited by the number of inputs to the crossbar. Simultaneously, the resistance of the memristors is kept constant at RON. The circuit's tolerance to the memristor variability and aging are analyzed, showing sufficient resilience. Also, the proposed recursive logic uses fewer cross-points, and has lower power dissipation than other memristive logic and CMOS implementation.

Analysis the several Techniques in designing the comparators for ADC converter and Introduction the CMOS Comparator Circuit with low power and high speed suitable for Medical Equipments

Analysis the several Techniques in designing the comparators for ADC converter and Introduction the CMOS Comparator Circuit with low power and high speed suitable for Medical Equipments

Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC

This paper presents a highly efficient ternary flash ADC, designed using the innovative gate-overlap tunnel FET (GOTFET) at the 45 nm technology node. The proposed GOTFETs have on-state currents Ion more than double, while the off-state currents Ioff remaining at least an order of magnitude lower than the corresponding values of the standard 45 nm CMOS technology with the same width. Replacing MOSFETs with the proposed GOTFETs significantly reduces the static power consumption and improves performance. However, the higher Ion increases the dynamic power as well. To minimize the dynamic power, we propose a novel complementary GOTFET (CGOT) based comparator design. In addition to the inherent advantages of the GOTFET technology, the proposed design further reduces the dynamic power, such that the final power delay product (PDP) is merely 6.3% of the PDP in conventional CMOS comparator design. In addition to the novelty related to the innovative GOTFET devices, there are at least two-fold circuit-level novelty reported in this work. Firstly, we propose a novel CGOT based comparator circuit design, which, in addition to the advantages of GOTFET, further reduces the dynamic power such that the PDP is less than 1/3rd of the original PDP of the conventional comparator designed with GOTFETs. Secondly, the proposed CGOT based ADC requires only 48 transistors to encode the comparator outputs into the 2-bit ternary output, which is 30% lower than the 70 transistors necessary for the 2-bit CMOS based ternary flash ADC designs reported earlier in the literature. We propose an efficient 2-bit ternary flash ADC with a resolution of 50 mV and input quantized to 9 levels. Subsequently, we benchmark the performance of the proposed CGOT ternary flash ADC with the same ADC circuit implemented using the standard 45 nm CMOS technology library, all corresponding devices having the same width. We demonstrate that in addition to the superior performance than the corresponding CMOS ADC, the proposed CGOT ADC design consumes significantly lower power. The overall PDP of the proposed CGOT ADC is merely 6.3% of the PDP in corresponding CMOS design.

A Successive Approximation Register Analog to Digital Converter for Low Power Applications

In recent years and continuing, widespread research work is carried out on medical implantable devices placed inside the human body. The essential and vital electronic circuit in implantable devices is the Analog to Digital Converter (ADC). The essential requirements in these applications such as long battery life-time, low power consumption and less die area poses a stringent requirement in designing and fabricating an ultra-low power ADCs. Among the diverse converter architectures existing, Successive Approximation Register (SAR) type converter architecture has shown better capabilities in terms of ultra-low power operation, medium resolution, less form factor and less silicon area. In this described paper a novel power effective, better resolution SAR type ADC to be used for biomedical related applications. The proposed work consists of capacitive type Digital to Analog Converter (DAC) based on charge distribution, a CMOS comparator, and SAR logic implemented using D-flip-flops. The different blocks of SAR architecture are simulated using EDA tools in CMOS 180 nm N-well process operated at VDD = 1.5 V voltage (VDD). The circuit is measured under various input frequencies with a sampling speed of 50 MHz and it consumes 22.6 μW. The proposed ADC technology shows SNDR of 48.6 dB and occupies a circuit area of 0.11 mm2 and the measured INL and DNL is calculated to be fewer than 0.54 LSB and 0.45 LSB respectively.

Cross Coupled Differential High Speed Comparator

Power efficiency and high speed comparator is presented. ,n-MOS transistors are used to design preamplifier stage and the latch stage. Both stages are controlled by a special clock circuit. By using clock circuit we can achieve enough preamplification gain. At the evaluation phase, the latch is activated with a delay to obtain sufficient pre-amplification gain and avoid extra power consumption. At this phase transistors are cross coupled to increase the preamplifier gain and to lower the input voltage common mode of the latch is used to strongly activate the n-MOS transistors (on the latch input) and reduce the delay. This circuit is designed with n-MOS transistors due to its inherent superiority over the p-MOS transistor. The proposed cross coupled comparator reduces the power and delay compared to conventional CMOS comparators.

Implementation of Double Tail Dynamic Latched Architecture for High Speed ADC

In this proposed work, a low offset voltage (mV) and high speed voltage comparator circuit is designed and simulated. With the unceasing rise of various wireless portable communication systems, high speed transceiver circuits, and high speed memory circuit design, sensitized sensor technologies, and wireless sensor network design, the design of high speed, low offset voltage and low power operated comparators are indispensable blocks in the design of a very good analog to digital converter architecture. The proposed work does not entail the usage of any pre-amplification stages, which accounts for the direct reduction of current consumption and silicon area. The MOSFETs at the input differential pair stage of the CMOS comparator circuit are designed to operate in near sub-threshold region rather than in saturation region to account for the low power consumption. The proposed double tail dynamic latched comparator in this work is implemented in 90μm CMOS technology with the operating power supply voltage (VDD) of 1.2 V and sampling frequency of 600 MHz using Microwind EDA tool. The simulated results indicate that the total power consumption is calculated to be of the order of 126.3μw with the delay of 876ps. From the obtained results, the proposed double tail dynamic latched circuit has considerably lowered both the propagation delay time and power consumption, when compared to the previous works.

Design and Simulation of 4-Bit Flash Analog to Digital Converter (ADC) for High Speed Applications

Objective: To design 4-bit flash Analog to Digital Converter (ADC) for high speed applications. The objectives of the project are to design sample and hold circuit, high efficient DAC circuit, to design a high speed, low power and minimum delay CMOS comparator and thermometer to binary code convertor logic. Methodology: The main block of flash ADC is designing of comparator. For high speed applications Flash ADC requires comparator having high sensitivity and low power dissipation. In this we have used CMOS comparator with cascaded stages, each stage will help in increasing gain and sensitivity and reducing the all types of noises. First stage is the pre-amplifier stage whose output is given to the input of decision stage. Decision stage is followed by post-amplifier stage. Findings: In most papers for designing flash ADC they used dynamic comparator, these dynamic comparators are more difficult to design and will give more power dissipation. In our design we used CMOS comparator with cascaded stages, this type of comparator provides less power dissipation, less delay and high sensitivity by reducing the noise like kickback noise, offset voltages etc. The design is simulated in 180 nm Technology with Cadence Virtuoso Tool and LT spice. Designed comparator has Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) error considered for design within +/- 0.5LSB. For N-bit flash ADC we have 2N-1 comparators, whose outputs will generate patterns of 0’s and 1’s in form of thermometer code; in order to convert it into binary format we have used mux encoder. This mux encoder logic reduces area and very easy to design compared to other methods. Applications/ Improvements: Flash ADC’s are used in various applications ranging from radar receivers, digital sampling, and LAN interface. The proposed design achieved a power dissipation of 0.121 mW with delay of 19.4 ns. The comparator block is designed and simulated. The sensitivity of the comparator is 0.003V. Keywords: CMOS Comparator, DNL and Binary Code Converter, Flash Analog to Digital Converter (ADC), Integral NonLinearity (INL)

Research and Construct of Low Power, Excessive-Velocity Comparators using Cmos Generation with Low Deliver Voltages for Adcs

The evaluation of many comparator outcomes for the given requirement having excessive velocity using analog to digital converters is growing, this are controlled using CMOS comparators which are successful when delivering the low voltage with high efficiency. The comparators are primary part of numerous simple to computerized converters. The prerequisite for low-control, rapid simple to advanced converters is increasing. Thus comparators are generally utilized in the present innovation because of its quick operational speed and high precision. The quickly developing versatile gadget requires low power and high operational capacities which should be improved. A concise investigation of traditional double tail voltage comparator is done and dependent on that, a low power and region productive comparator is displayed. Another comparator is planned so as to decrease the postponement of ordinary comparators and diminish the power utilization of the gadget. Furthermore, the Reproduction is finished by Leather Treated Simple Plan Condition. At last we study about conventional dual tail voltage comparator which is done based on low power and area efficient comparator. In this simulation of proposed comparator is occurs a 180nm CMOS technology its consumes the power of 69μW at 1.2v Ac power supply voltage.

A nanoscale gate overlap tunnel FET (GOTFET) based improved double tail dynamic comparator for ultra-low-power VLSI applications

This paper introduces an innovative Gate Overlap Tunnel FET (GOTFET) device which is an advanced TFET engineered to yield double the on current $$I_{\mathrm{on}}$$ , while the off current $$I_{\mathrm{off}}$$ remains an order lower than the analogous MOSFET having same width at the same technology node. A conventional Dynamic Comparator designed using the proposed Complementary GOTFET (CGOT) paradigm exhibits 93 ps (25%) lower delay than similar CMOS designs and consumes merely 1.11 pW (99% lower than CMOS) of static power. The overall power delay product (PDP) in the CGOT comparator design has been shown to be only 0.5% of the PDP of a conventional CMOS comparator. Although the advantages of higher $$I_{\mathrm{on}}$$ are manifold, however, it increases dynamic power as well. So this paper goes beyond device-level improvisation and proposes for the first time, a novel improved comparator circuit designed using the CGOT paradigm which further reduces the total power by an additional 44.5%.

Analysis of different comparator architectures

Comparators are very important and essential circuits in the implementation of analog to digital converter (ADC) architectures. In this work, three different types of CMOS comparator architectures namely single tail type, double tail dynamic latch type and fully differential dynamic type have been designed, simulated and various specifications have been compared and analyzed. From the obtained results, the double tail dynamic latch type comparator offers better performance in terms of delay, power dissipation and offset voltage measurement. The three architectures are designed and simulated in CMOS 90nm technology using spectre of cadence EDA tool. The main specifications considered are power dissipation, gain, propagation delay, offset voltage and slew rate. The double tail dynamic latch type comparator operated at a power supply voltage of 1.2V, exhibits an offset voltage of 7.34mV, dissipates power of 136µW with a delay of 526ps.

Design and Analysis of High Gain Low Power CMOS Comparator

Design and Analysis of High Gain Low Power CMOS Comparator

Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques

To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 μW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 μW while CVSL shows total power consumption of 18.94 μW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology.

An Optimal Design of CMOS Two Stage Comparator Circuit using Swarm Intelligence Technique

A swarm intelligent based optimization technique named as Flower pollination algorithm (FPA) is applied for the design of the CMOS two stage comparator circuit. The basic idea of FPA mimics the flower pollination process of flowering plants. The input control parameters of FPA improve the exploration and exploitation capabilities of optimization problem. This paper presents the design of a CMOS two-stage comparator circuit using simulation based model called swarm intelligence technique. Simulation results shows that the proposed method is capable to determine the transistor sizes and bias current values of the CMOS comparator. The results obtained from the FPA improved the design performance of comparator in terms of power consumption, MOS transistor area and gain. To investigate the efficiency of proposed approach, comparisons have been carried out with differential evolution (DE) and harmony search (HS) algorithm based circuit design. The performances of FPA based comparator design are better than the previously reported works

An Optimal Design of CMOS Two Stage Comparator Circuit using Swarm Intelligence Technique

A swarm intelligent based optimization technique named as Flower pollination algorithm (FPA) is applied for the design of the CMOS two stage comparator circuit. The basic idea of FPA mimics the flower pollination process of flowering plants. The input control parameters of FPA improve the exploration and exploitation capabilities of optimization problem. This paper presents the design of a CMOS two-stage comparator circuit using simulation based model called swarm intelligence technique. Simulation results shows that the proposed method is capable to determine the transistor sizes and bias current values of the CMOS comparator. The results obtained from the FPA improved the design performance of comparator in terms of power consumption, MOS transistor area and gain. To investigate the efficiency of proposed approach, comparisons have been carried out with differential evolution (DE) and harmony search (HS) algorithm based circuit design. The performances of FPA based comparator design are better than the previously reported works

VLSI Design of Low Power 4 Bit Magnitude Comparator Using GDI Technique

Now a days Low power, delay play a very important role in emerging technologies. To reduce power consumption and propagation delay involved in the circuit , the paper presents GDI technique for implementation of digital logic circuit . In this paper ,4 bit magnitude comparator is designed using conventional CMOS logic style and GDI technique. The proposed GDI magnitude Comparator requires 127 transistors and implementation using CMOS logic requires 226 transistors. The power consumed by the 4 bit magnitude CMOS comparator is 276.50μw and the power consumed by the 4 bit GDI comparator is 21.97μW which is very less as compared to conventional CMOS Style. Delay present in the conventional CMOS magnitude comparator is in 150μsec whereas the delay produced by GDI technique for magnitude comparator 74μsec. Delay is also reduced in the proposed GDI technique. Thus proposed GDI technique shows 92.05% efficiency for power measurement. All this circuit simulation is done by using TANNER TOOL EDA version 13.1 at 180 nm process technology.