VLSI Design of Low Power 4 Bit Magnitude Comparator Using GDI Technique

Abstract

Now a days Low power, delay play a very important role in emerging technologies. To reduce power consumption and propagation delay involved in the circuit , the paper presents GDI technique for implementation of digital logic circuit . In this paper ,4 bit magnitude comparator is designed using conventional CMOS logic style and GDI technique. The proposed GDI magnitude Comparator requires 127 transistors and implementation using CMOS logic requires 226 transistors. The power consumed by the 4 bit magnitude CMOS comparator is 276.50μw and the power consumed by the 4 bit GDI comparator is 21.97μW which is very less as compared to conventional CMOS Style. Delay present in the conventional CMOS magnitude comparator is in 150μsec whereas the delay produced by GDI technique for magnitude comparator 74μsec. Delay is also reduced in the proposed GDI technique. Thus proposed GDI technique shows 92.05% efficiency for power measurement. All this circuit simulation is done by using TANNER TOOL EDA version 13.1 at 180 nm process technology.