Analysis of different comparator architectures

Abstract

Comparators are very important and essential circuits in the implementation of analog to digital converter (ADC) architectures. In this work, three different types of CMOS comparator architectures namely single tail type, double tail dynamic latch type and fully differential dynamic type have been designed, simulated and various specifications have been compared and analyzed. From the obtained results, the double tail dynamic latch type comparator offers better performance in terms of delay, power dissipation and offset voltage measurement. The three architectures are designed and simulated in CMOS 90nm technology using spectre of cadence EDA tool. The main specifications considered are power dissipation, gain, propagation delay, offset voltage and slew rate. The double tail dynamic latch type comparator operated at a power supply voltage of 1.2V, exhibits an offset voltage of 7.34mV, dissipates power of 136µW with a delay of 526ps.