Abstract
This paper proposed a design of low-voltage Dynamic Comparator using 90 nm PTM CMOS technology for high-speed and Lower-power Analog to Digital Converter (ADC) applications. The double tail structure is employed as based for design new comparator with positive feedback due to best behavior in low-voltage that allows low delay time; decreases the offset voltage and power dissipation. Simulation results are presented with sampling frequency of 10GHZ. These results are also compared with earlier works interms of their delay time, power dissipation and offset voltage. The proposed comparator shows 5.7 mV offset which is small when compared to other dynamic comparators and preamplifier based comparators.
Highlights
The function of a comparator is to generate an output voltage whose value is high or low depending on the amplitude of the input
Dynamic comparators are widely used in high-speed Analog to Digital Converter (ADC) because of its low power consumption and high speed
Designed voltage comparator consists of three stages: Input stage, decision stage and output stage (Mongre and Gurjar, 2014) and the performance of any comparator is defined by the characteristic parameters such as offset voltage (Shaik and Rajesh, 2013), kickback noise (Pedro and Vital, 2006), clock frequency or speed (Iniewski, 2015), low-power consumption (Zbigniew, 2016), high resolution and random noise (Dastagiri and Hari Kishore, 2018)
Summary
The function of a comparator is to generate an output voltage whose value is high or low depending on the amplitude of the input. Designed voltage comparator consists of three stages: Input stage, decision stage and output stage (Mongre and Gurjar, 2014) and the performance of any comparator is defined by the characteristic parameters such as offset voltage (Shaik and Rajesh, 2013), kickback noise (Pedro and Vital, 2006), clock frequency or speed (Iniewski, 2015), low-power consumption (Zbigniew, 2016), high resolution and random noise (Dastagiri and Hari Kishore, 2018). A conventional double-tail comparator is shown in Fig. 3 (Dastagiri and Hari Kishore, 2018; Rajesh et al, 2016) This circuit enables a large current in the latching stage for fast speed and problems in low power supply voltage, offset input common-mode voltage due to its structure can be overcome, but this comparator requires high accuracy timing between CLKA and CLKB. MC1 and MC2 provide additional shielding between the input and output, which in turn reduces kickback noise
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