Thermally Aware Modeling and Performance Analysis of MLGNR as On-Chip VLSI Interconnect Material

Abstract

In this study, a thermally aware electrical equivalent single conductor along with an analytical model to evaluate the parasitic parameters of multilayer graphene nanoribbon (MLGNR) as an on-chip very-large-scale integration interconnect is proposed and its performance is analyzed in terms of delay, power dissipation, and power delay product (PDP) with variable temperatures ranging from 200 K to 500 K for 32 nm, 22 nm, and 16 nm technology nodes. It was observed that with a rise in the temperature, there is a sharp decrease in the mean free path of the GNR interconnect, which further dominates its own resistance at variable global lengths (500–2000 μm) for all three technology nodes. The Simulation Program with Integrated Circuit Emphasis (SPICE) simulation tool is used to estimate and compare the performance of MLGNR in terms of signal delay, power dissipation, and PDP for three different technology nodes. It is revealed from the results that the propagation delay and PDP increase with increasing temperature. A similar analysis was also done for the copper interconnect and it was found that the MLGNR gives better performance in terms of delay, power dissipation, and PDP, at long interconnects (2000 μm) over a temperature range of 200–500 K for deep submicron technology nodes (32 nm, 22 nm, and 16 nm).