Abstract
Design and Analysis of High Gain Low Power CMOS Comparator
Highlights
The comparator is the key building block in the design process of ADC, which controls the performance and the accuracy of ADCs
A modified comparator is presented, which is based on two-stage differential amplifier input stages. This modified design has a level shifting stage, which is capable of providing higher gain with lower power consumption and lower power supply compared to other topologies based on the simulation result
Since the phase margin is often traded with a higher gain, in this research the designed comparator circuit can maintain the phase margin at 60.08°, which is the typical value for a comparator to operate in a stable condition
Summary
The design consideration of the comparator includes gain, offset voltage, phase margin, slew rate, settling time and power dissipation [13]. The modified design has three stages, current source, two-input differential mode amplifier and common source amplifier. The second stage consists of a two-input differential mode amplifier with single-ended output, which can provide higher gain, CMRR, PSRR, slew rate and lower power consumption. This stage converts the differential input voltage to the current output, which is subsequently applied to a current mirror load. The last stage consists of common source amplifier to perform level shifting, gain boosting, and current to voltage conversion with the single output voltage. All transistors and capacitors are placed in a manner that reduces the mismatch and parasitic capacitance
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