Cross Coupled Differential High Speed Comparator

Abstract

Power efficiency and high speed comparator is presented. ,n-MOS transistors are used to design preamplifier stage and the latch stage. Both stages are controlled by a special clock circuit. By using clock circuit we can achieve enough preamplification gain. At the evaluation phase, the latch is activated with a delay to obtain sufficient pre-amplification gain and avoid extra power consumption. At this phase transistors are cross coupled to increase the preamplifier gain and to lower the input voltage common mode of the latch is used to strongly activate the n-MOS transistors (on the latch input) and reduce the delay. This circuit is designed with n-MOS transistors due to its inherent superiority over the p-MOS transistor. The proposed cross coupled comparator reduces the power and delay compared to conventional CMOS comparators.