CMOS Applications Research Articles

Development of Data Concentration Method and Its Implementation in a Radiation-Tolerant CMOS Application Specific Integrated Circuit

Development of Data Concentration Method and Its Implementation in a Radiation-Tolerant CMOS Application Specific Integrated Circuit

Poisson-Schrödinger simulation and analytical modeling of inversion charge in FDSOI MOSFET down to 0 K – Towards compact modeling for cryo CMOS application

Poisson-Schrödinger (PS) simulations and an analytical charge model for a back biased FDSOI structure operated at deep cryogenic temperatures have been developed. PS simulations have been conducted down to 0 K, where metallic statistics applies, by replacing the F0 Fermi integral by a Heaviside function. Considering, as a first approximation, two separated channels for front and back interface, a set of implicit equations has been established based on a single subband scheme within the Airy approach, providing a good description of surface potential, inversion charge and capacitance characteristics of FDSOI structures operated at very low temperature and for various back biases and silicon thicknesses. This analytical charge model is a first step towards a compact model of FDSOI MOSFET for circuit design at cryogenic condition.

Study of Nanowire-Based Integrated via Technology for CMOS Application in Millimeter-Wave Frequencies

This work shows a novel integrated via structure based on 1.2- μm thick copper nanowires (NWs) for use in CMOS applications at millimeter-wave frequencies. Coplanar waveguide (CPW) lines are fabricated on a 5000-Ω-cm high-resistivity silicon wafer and connected by NW vias that are grown in integrated anodized alumina oxide (AAO). The AAO layer is fabricated by anodizing an evaporated aluminum layer onto the silicon wafer. This cointegrated technology has 0.095-dB insertion loss for 0.3-mm long circuits with two vias at 40 GHz. The results are promising with an estimated loss per via of approximately 0.0275 dB. The fabricated structure shows great performance agreement with its reference test circuits of similar length. The design comparisons of circuits with different via dimensions and positions show that the shorter the via length, the wider the via width; and placing the via on the CPW ground plane closer to the signal line provides better performance.

Investigation on surface smoothing of silicon-on-insulator with gas phase hydrogen chloride etching

Silicon-on-insulator (SOI) substrates are widely used in integrated circuit manufacture because of the advantages of SOI devices. To obtain smooth and uniform top silicon layer, the process of smoothing and thinning becomes more and more critical. Surface smoothing and thinning of top silicon layer of SOI are achieved by applying gas phase hydrogen chloride etching. In this work, gas mixture with HCl proportion below 1% is used to etch the top silicon layer at various conditions. Etch rate is influenced by HCl proportion and gas flow, however, the etch rate almost keeps constant at the temperature range between 1000 °C and 1100 °C. Root mean square roughness value of etched sample can be lower than 0.2 nm, which is close to the value of bare silicon substrate, and could satisfy the requirements of CMOS applications.

Hardware architecture for real-time EEG-based functional brain connectivity parameter extraction

Objective. Design a novel architecture for real-time quantitative characterization of functional brain connectivity (FC) networks derived from wearable electroencephalogram (EEG). Approach. We performed an algorithm to architecture mapping for the calculation of phase lag index to form the functional connectivity networks and the extraction of a set of graph-theoretic parameters to quantitatively characterize these networks. This mapping was optimized using approximations in the mathematical definitions of the algorithms which reduce its computational complexity and produce a more hardware amenable implementation. Main results. The architecture was developed for a 19-channel EEG system. The system can calculate all the functional connectivity parameters in a total time of 131 µs, utilizes 71% of the total logic resources in the FPGA, and shows 51.84 mW dynamic power consumption at 22.16 MHz operation frequency when implemented in a Stratix IV EP4SGX230K FPGA. Our analysis also showed that the system occupies an area equivalent to approximately 937 K 2-input NAND gates, with an estimated power consumption of 39.3 mW at 0.9 V supply using a 90 nm CMOS application specific integrated circuit technology. Significance. The proposed architecture can calculate the FC and extract the graph-theoretic parameters in real-time with low power consumption. This characteristic makes the architecture ideal for applications such as a wearable closed-loop neurofeedback systems, where constant monitoring of the brain activity and fast processing of EEG is necessary to control the appropriate feedback.

Extending the resolution limits of nanoshape imprint lithography using molecular dynamics of polymer crosslinking

Emerging nanoscale applications in energy, electronics, optics, and medicine can exhibit enhanced performance by incorporating nanoshaped structures (nanoshape structures here are defined as shapes enabled by sharp corners with radius of curvature < 5 nm). Nanoshaped fabrication at high-throughput is well beyond the capabilities of advanced optical lithography. Although the highest-resolution e-beams and large-area e-beams have a resolution limit of 5 and 18 nm half-pitch lines or 20 nm half-pitch holes, respectively, their low throughput necessitates finding other fabrication techniques. By using nanoimprint lithography followed by metal-assisted chemical etching, diamond-like nanoshapes with ~3 nm radius corners and 100 nm half-pitch over large areas have been previously demonstrated to improve the nanowire capacitor performance (by ~90%). In future dynamic random-access memory (DRAM) nodes (with DRAM being an exemplar CMOS application), the implementation of nanowire capacitors scaled to <15 nm half-pitch is required. To scale nanoshape imprint lithography down to these half-pitch values, the previously established atomistic simulation framework indicates that the current imprint resist materials are unable to retain the nanoshape structures needed for DRAM capacitors. In this study, the previous simulation framework is extended to study improved shape retention by varying the resist formulations and by introducing novel bridge structures in nanoshape imprinting. This simulation study has demonstrated viable approaches to sub-10 nm nanoshaped imprinting with good shape retention, which are matched by experimental data.

Study and Analysis of Advanced 3D Multi-Gate Junctionless Transistors

As the IC technology is evolving very rapidly, the feature size of the device has been migrating to sub-nanometre regime for achieving the high packing density. To continue with further scaling of ICs, some novel devices such as multiple-gate silicon-on-insulator (SOI) devices, Gate-All-Around (GAA) nanowire and Nanotube MOSFETs have been proposed by researchers in recent years. The short channel transistor below 10 nm needs to have ultra-sharp junctions at source and drain ends with the channel region. The creation of such a sharp junction is quite challenging process from fabrication point of view. Therefore, junctionless transistors (JLT) were proposed to eradicate junction’s related issues, exhibit full CMOS functionality. The multigate junctionless transistors have been proposed, designed and fabricated. This paper illustrated basic working mechanism and behaviour of the various single and multi-gate junctionless MOSFETs. Junctionless nanowires transistor with single circular gate and gate material engineered techniques has also been explained. From simulation results, it has been observed that junctionless Nanotube GAA MOSFET has shown superior electrical behaviour over the Nanowire GAA MOSFET. Junctionless GaAs-Nanotube MOSFET has shown tremendous response over Junctionless Si-Nanotube MOSFET in terms of leakage and ON current. Junctionless GaAs-Nanotube MOSFET may be observed as alternate candidate for future CMOS applications.

An extensive survey on future direction for the reduction of noise coupling problem in TSV based 3-dimensional IC integration

Over the period of meticulous scaling IC’s are crucially waiting for a platform which is planar. The most important and actual restriction is nothing, but delay of interconnect is almost approximate to that of devices. To achieve the demands of system performance, new interconnecting materials along with experimental architectures need to be developed. A new integration approach is developed which is nothing but 3D integration technology because this technology is most advantageous and famously used in comparisons to other technologies. Also 3-D technology has a capacity to ensemble with CMOS application because it can easily connect many devices in layers and can be stacked vertically with interconnecting wires having higher thickness among the layers. In this TSV’s plays an important job, which can enable 3-D IC platform. Noise coupling from TSV-to-TSV and TSV-to-Substrate is estimated inside the heterogeneous integration. A vertical TSV pattern is developed to decrease the area per TSV, capacitive coupling and make constructive inductance compared to other design patterns. By developing the vertical TSV patterns in 3D IC the functionality became easier with lesser TSV’s.

Vertically Stacked High Mobility GeSi nGAAFETs

Si FinFET architecture has been used in mass production in the industry for advanced technology nodes. Thin and tall fin for high drive current is needed for further scaling by FinFETs. However, fin aspect ratio and lithography limitation may be problematic issues. Recently, vertically stacked channel GAAFETs become good candidates to achieve better power-performance properties than FinFETs for the given footprint. The evolution to the stacked GAAFETs mitigates the patterning challenges by well-controlled epitaxy and high etching selectivity to achieve high performance and good electrostatics. The state-of-the-art stacked Si channel n/pGAAFETs and stacked Ge channel pGAAFETs have been reported. In this study, we demonstrate vertically stacked tensily strained GeSi nGAAFETs. The stacked GeSi nGAAFETs provide a possible solution to achieve high performance and to improve the electrostatics for Ge-based channel GAAFETs.The Ge/Ge0.85Si0.15 and Ge/Ge0.98Si0.02 multilayers are epitaxially grown on SOI substrates by CVD epitaxy. Ge buffer layers and sacrificial layers are not only used to achieve etching selectivity over GeSi layers to form the vertically stacked GeSi channels, but also used to provide tensile strain for GeSi n channels. Undoped channels and heavily doped sacrificial layers are used to reduce the impurity scattering and S/D resistance, respectively. The following PMA, laser annealing, and NiGe contacts formation for nFETs can further reduce the parasitic resistance to reveal the intrinsic merit of the high mobility GeSi channels.For GeSi nFETs, [Ge] larger than 85% in GeSi can ensure L valley conduction for small conductive effective mass to achieve high mobility. The △Ec between GeSi and Si is nearly zero and can be negligible. As a result, electron can flow through stacked GeSi channels and Si channel underneath for the nFETs. An engineering solution is provided to improve the electrostatic behaviors of Ge-based channels GAAFETs. We demonstrate the vertically stacked Ge0.85Si0.15 channels above a Si channel, which has good subthreshold behaviors. The VT difference between Ge0.85Si0.15 and Si can be tuned by the channel size optimizing. By narrowing the Ge0.85Si0.15 channel size to 5nm, the bandgap can be increased by quantum confinement and the short channel effect can be suppressed. As a result, more positive VT for Ge0.85Si0.15 than Si is observed. Therefore, the underneath Si channel with good electrostatic turn on first and dominate the subthreshold region. Good SS=76mV/dec and low DIBL=36mV/V are obtained due to low Dit and good short channel control. IOFF is also dramatically reduced and the ION/IOFF is improved to be 1.2E7 thanks to the increase of the bandgap and the improved short channel control for the narrow Ge0.85Si0.15 channels. The improved flicker noise of optimized channel size also indicates the enhanced reliability.To increase [Ge] in channel layers for mobility enhancement, Si incorporation as small as 2% into Ge can achieve sufficient etching selectivity of heavily phosphorus-doped Ge sacrificial layers over undoped Ge0.98Si0.02 to form two stacked Ge0.98Si0.02 nanowire channels, and introduce 0.27% uniaxial tensile strain for the electron mobility enhancement. The alloy scattering is still minimal for 2% Si. An additional 800oC anneal after the Ge buffer growth further improves the epi quality by confining misfit dislocations near the Ge buffer/Si interface. However, the Dit at Si underneath channel/dielectrics interface may be poor due to misfit dislocations confinement. As a result, the parasitic Ge/Si channel underneath the Ge0.98Si0.02 channels is completely removed by optimized etching. The distinct photoresponse of the floating channels and the parasitic channels can be a signature and provide a non-destructive method to check the existence of the parasitic channels. The photoresponse of the sole parasitic channel mainly shows the photocurrent (Iph), while the photoresponse of the sole floating channels without parasitic channel yields the negative threshold voltage shift (ΔVT) for nFETs. The device with both floating channels and the parasitic channel shows both photocurrent and negative threshold voltage shift under exposure. ION can be enhanced by scaled LG and large channel cross section. Record ION of 48μA per stack at VOV=VDS=0.5V and record Q (Gm,max/SSSAT) of 8.3 at VDS=0.5V with LG=40 nm are achieved among Ge nFETs.CVD grown Ge nGAAFET is compatible with Si technology. Excellent electrical characteristics are achieved and the results are comparable to mature Si nFETs. Indicating vertically stacked high mobility channel is promising candidate for CMOS applications in the future technology nodes to further extend the Moore’s law.Acknowledgements: This work is supported by MOST (MOST 109-2218-E-002-031- and 108-2622-8-002-016-) and MOE (NTU-CC-109L891601), Taiwan. The support from Taiwan Semiconductor Research Institute is also highly appreciated.

Plasma Etching of Polycrystalline Silicon using Thinning Technology for Application in CMOS and MEMS Technologies

This work presents results of the study of profile evolution for Si-poly structures during plasma etching using the thinning technology in SF6/CF4/CHF3 gas mixtures. Structures with an aspect ratio (height/width) up to 5, widths end in the range of 0.3 – 0.1 μm and 0.3μm thick, were produced. Sipoly structures with high anisotropy (anisotropy factor up to 0.92-0.98) after etching were demostrated. The method can be used for fabrication of sub-micron Si-poly gates in CMOS and in fabrication of MEMS devices.

A 0.85mm2 BLE Transceiver Using an On-Chip Harmonic-Suppressed RFIO Circuitry With T/R Switch

This article presents a small-area Bluetooth Low-Energy (BLE) transceiver (TRX) for short-range Internet-of-Things (IoT) applications in 65-nm CMOS. An integrated Radio-Frequency Input-Output (RFIO) circuitry embedded with transmitter/receiver (TX/RX) switch function and on-chip impedance matching is proposed. A hybrid-loop TRX structure based on a wide-bandwidth fractional-N digital phase-locked loop (DPLL) is implemented to achieve the maximum power reduction. A -94dBm receiver sensitivity is achieved with 2.3mW receiver power consumption, while a RF receiving bypass route integration enhances the input power tolerance. The BLE transceiver delivers -6dBm output power while consuming 2.6mW and delivers 0dBm output power while achieving 18.5% maximum TX efficiency. Thanks to the RFIO with harmonic suppression, -56dBc of 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -order harmonic distortion (HD2) and -48dBc of 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> -order harmonic distortion (HD3) suppression are achieved with 0.85mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> on-chip area. This transceiver satisfied the BLE radio specification without the need for external filters and with low-power consumption, which enables minimum size and long life-time modules.

Influence of oxygen source on the ferroelectric properties of ALD grown Hf1-xZrxO2 films

Hafnium oxide (HfO2), zirconium oxide (ZrO2), and the solid-solution (Hf1-xZrxO2) system continue to be some of the most relevant ferroelectric materials, in particular, for their promising application in CMOS integrated ferroelectric memories. Recent understanding of the influence of oxygen supplied during film deposition on the structural phase formation process in Hf1-xZrxO2 films has drawn attention to a commonly overlooked parameter for tuning ferroelectric and electrical properties of these films. In this paper, a comparison of O3 and O2 plasma used as the oxygen source in an atomic layer deposition process for Hf1-xZrxO2 films within the full compositional range is discussed. A combination of structural and electrical characterization methods grant insight on the influence of each of the oxygen sources on the crystalline phase formation during deposition of Hf1-xZrxO2 films. These observations are then correlated to the material’s behavior regarding its ferroelectric and electrical properties; mainly, dielectric constant, ferroelectric remanent polarization, and number of electric field cycles to breakdown.

Thermal management in TSV based 3D IC Integration: A survey

Three Dimensional IC (3D IC) integration is one of the emerging technology which suits CMOS applications by stacking various IC layers vertically. In 3D IC, IC Layers are interconnected electrically using Through Silicon Vias (TSV’s) and mechanically by Cu–Cu bonding. The major drawbacks in 3D IC structures are thermal issues between layers and noise coupling between TSV-to-substrate and TSV-to-TSV which leads significantly on the overall system performance. This paper presents an extensive survey on one of the major issue in 3D based IC integration technique called thermal issues between the layers and how the researchers have tried to overcome the problems by introducing various materials which are suitable for elimination of hotspot, by introducing spreaders among the layers. This extensive survey work shows the complete roadmap for the thermal management in future IC Integration.

An extensive survey on reduction of noise coupling in TSV based 3D IC integration

3D Integration technology is probably the best methodologies among others which suits CMOS applications with in various layers of devices are stacked with high thickness interconnects between the layers. In 3D IC structure electrical and thermal models are introduced for the interface between Through-Silicon-Via’s (TSV’s). TSV’s can be used to enable the 3-D platform; however this TSV’s will represent additional concerns. TSV-to-substrate and TSV-to-TSV noise coupling is assessed inside the 3-D IC’s. A vertical TSV’s design is proposed to reduce the area per TSV, capacitive coupling and effective inductance as compared with the other classical design patterns. TSV’s and substrate noise coupling is one of the major drawbacks in 3D IC. Some of the researchers have tried to overcome the problems in TSV based 3D IC due to noise coupling using different models, materials and different circuit techniques. This paper shows the complete road map for the noise coupling reduction in future IC integration.

Ferroelectric HfO2 Capacitors for Varactor Application in GHz

Capacitance extraction of ferroelectric HfO2 capacitors was characterized at a frequency of 1 GHz. By applying a bias voltage in the non-switching region of the ferroelectric HfO2 films, a varactor operation was confirmed. Introduction The ferroelectric HfO2 layer has attracted attraction in CMOS and memory applications due to its scaling ability and process compatibility. Generally, ferroelctric capacitors show increase in the capacitance near the coercive field. By setting a proper bias to the ferroelectric capacitors, they can work as varactors under non-switching mode. As there is an increasing demand on-chip varactors for monolithic microwave ICs (MMICs) [1,2]. In this research, we measured the capacitance of the ferroelectric HfO2 capacitors at high frequency and confirmed the capacitance control. Measruements were done under on-wafer probing system in the frequency range of 10 MHz to 1 GHz [3]. Experiments Figure 1 shows the schematic cross-section of ferroelectric HfO2 capacitors. A 1 mm plasma SiO2 layer was first deposited on a high-resistive Si wafer f. A 12-nm-thick 5 mol% Y-doped HfO2 film were deposteid by atomic layer deposition (ALD). The top and bottom electrode were both W deposited by sputtering and patterned by reactive ion etching (RIE). Annealing to transform the HfO2 layer into ferroelectric pahse was conducted at 500 oC. Metal contacts of Au/Ni/Ti were deposited by thermal evaporation. Results and discussions Capacitance-voltage measurement taken from LCR meter at 10 kHz is shown in fig. 2. After polling process, the capacitance can be tuned by 32 % by controlling the bais voltage in the non-switching region. The capacitance values under different bias voltage, extracted from the S-parameters of capacitors with proper calibration patterns, are shown in fig. 3. Although the capacitance tuning was narrow compared to those obtained by the LCR meter, the varactor operation was confirmd with ferroelectric HfO2 capacitors. Conclusion A varactor operation in ferroelectric HfO2 capacitor at 1 GHz was confirmed.

On-Chip Fully Integrated Field Emission Arrays for High-Voltage MEMS Applications

Vacuum-sealed fully integrated diode and triode field emission arrays based on Ti Spindt-type field emitters have been developed in a scalable, CMOS-compatible process directly on Si. Diode characterization in air demonstrates effective vacuum sealing and field emission conduction, with current drivability that scales with array size. Triode characterization in vacuum demonstrates gate-modulated field emission of the output current and highlights new effects observed in a fully integrated geometry with closely spaced electrodes. Demonstrating up to 200-V blocking voltage and similar magnitude punchthrough voltages, the arrays can be utilized as high-voltage devices in CMOS applications or with microelectromechanical systems (MEMS) technologies using post-CMOS MEMS integration techniques. Low-temperature measurements reveal areas of improvement for electrode isolation; combined with the use of improved cathode materials, these devices have the potential to be used in high-power applications.

Indium-Tin-Oxide Transistors with One Nanometer Thick Channel and Ferroelectric Gating.

In this work, we demonstrate high-performance indium-tin-oxide (ITO) transistors with a channel thickness down to 1 nm and ferroelectric Hf0.5Zr0.5O2 as gate dielectric. An on-current of 0.243 A/mm is achieved on submicron gate-length ITO transistors with a channel thickness of 1 nm, while it increases to as high as 1.06 A/mm when the channel thickness increases to 2 nm. A raised source/drain structure with a thickness of 10 nm is employed, contributing to a low contact resistance of 0.15 Ω·mm and a low contact resistivity of 1.1 × 10-7 Ω·cm2. The ITO transistor with a recessed channel and ferroelectric gating demonstrates several advantages over 2D semiconductor transistors and other thin-film transistors, including large-area wafer-size nanometer thin-film formation, low contact resistance and contact resistivity, an atomic thin channel being immune to short channel effects, large gate modulation of high carrier density by ferroelectric gating, high-quality gate dielectric and passivation formation, and a large bandgap for the low-power back-end-of-line complementary metal-oxide-semiconductor application.

Atomic layer deposition of SiO2–GeO2 multilayers

Despite its potential for CMOS applications, atomic layer deposition (ALD) of GeO2 thin films, by itself or in combination with SiO2, has not been widely investigated yet. Here, we report the ALD growth of SiO2/GeO2 multilayers on si1icon substrates using a so far unexplored Ge precursor. The characterization of multilayers with various periodicities reveals layer-by-layer growth with electron density contrast and the absence of chemical intermixing, down to a periodicity of two atomic layers.

Athermal Polysilicon Mach-Zehnder Interferometer in Bulk CMOS

This study demonstrates the first athermal polysilicon Mach-Zehnder interferometer (MZI) based on strip and subwavelength grating waveguides in commercialized bulk CMOS without any process modification. As-fabricated MZI exhibits a temperature sensitivity of ±4 pm/°C over 1500~1600 nm wavelength range with a slope of -0.055 pm/°C/nm. This wavelength filtering device is therefore immune from the temperature gradient issue arising from the nearby electronic circuits, thus is promising for practical on-chip optical interconnect and sensor applications in bulk CMOS.

Switching Dynamics Measurement of Ferroelectric Y-Doped HfO2 M-I-M Capacitor

Domain-switching kinetics of 5 mol% Y-doped HfO2 metal-insulator-metal (MIM) capacitor was characterized. The changes in polarization indicate the polarization reversal in HfO2. In this research, we show the polarization reversal of an 20-nm-thick Y-doped HfO2 deposited by atomic layer deposition (ALD) by switching the applied voltage (2.6 to 4.6V) and the pulse duration (1μs to 500μs). We use the measurements of Kolmogorov-Avrami-Ishibashi (KAI) model to extract the minimum switching time of the domains. Introduction Ferroelectric HfO2 layer has attracted attraction in CMOS and memory applications owing to its scaling ability and process compatibility. It has been demonstrated that doping of foreign elements, including Zr, Si, Al, Y, atoms under post-deposition annealing (PDA) or post-metallization annealing (PMA) induces the ferroelectricity in HfO2 [1]. The switching dynamics of ferroelectric Al- and Zr-doped HfO2 metal-insulator-metal (MIM) capacitors has been well-modeled by nucleation limited switching (NLS) model, where multigrain polarization takes place assuming a distribution in the switching time [2, 3]. In this study, we apply the KAI model to fit the switching dynamics of Y-doped HfO2 MIM capacitor using the following equation,, △P=Ps*(1-exp{-(t/τ)β })where △P, P s, τ and β are the partial, saturation polarization, switching time constant and a fitting parameter, respectively [4]. Experiments An MIM capacitor with a 20-nm-thick 5 mol% Y-doped HfO2 film was fabricated by atomic layer deposition (ALD). The top and bottom electrode were both W deposited by sputtering. PMA was then carried out at 500 oC for 1 minute. Typical polarization-voltage (P-V) hysteresis is shown in fig. 1, where a remanent polarization (P r) of 12 mC/cm2 was obtained. A voltage waveform shown in fig. 2 was applied to the electrode to measure the polarization reversal of the devices after certain polling process. Polarization reversal was extracted by applying pulses with various height ranging from 2.6 to 4.6 V and width from 1 ms to 500 ms followed by half P-V measurement. Results and discussions Fig 3 shows measured partial polarization with different pulse width and voltage. As the pulse width increases, △P increases, indicating that a certain time is required to fully switch the domains. Data fit using the KAI model has well reproduced the measured data, indicating the presence of multigrain switching. However, a β of 0.6 to 0.8, which is smaller than those of Zr-doped HfO2 (typically b=2.1), needs to be used to fit the data. This may imply the difference in the domain size among dopants incorporated in the HfO2 layer. Conclusion Switching dynamics of ferroelectric Y-doped HfO2 MIM capacitors has been measured. The device has shown to follow the multidomain switching based on KAI model as is explained for Zr-doped HfO2 ones, except for the difference in the fitting parameter.