Clock Tree Research Articles

Assessing the effect of model specification and prior sensitivity on Bayesian tests of temporal signal.

Our understanding of the evolution of many microbes has been revolutionised by the molecular clock, a statistical tool to infer evolutionary rates and timescales from analyses of biomolecular sequences. In all molecular clock models, evolutionary rates and times are jointly unidentifiable and 'calibration' information must therefore be used. For many organisms, sequences sampled at different time points can be employed for such calibration. Before attempting to do so, it is recommended to verify that the data carry sufficient information for molecular dating, a practice referred to as evaluation of temporal signal. Recently, a fully Bayesian approach, BETS (Bayesian Evaluation of Temporal Signal), was proposed to overcome known limitations of other commonly used techniques such as root-to-tip regression or date randomisation tests. BETS requires the specification of a full Bayesian phylogenetic model, posing several considerations for untangling the impact of model choice on the detection of temporal signal. Here, we aimed to (i) explore the effect of molecular clock model and tree prior specification on the results of BETS and (ii) provide guidelines for improving our confidence in molecular clock estimates. Using microbial molecular sequence data sets and simulation experiments, we assess the impact of the tree prior and its hyperparameters on the accuracy of temporal signal detection. In particular, highly informative priors that are inconsistent with the data can result in the incorrect detection of temporal signal. In consequence, we recommend: (i) using prior predictive simulations to determine whether the prior generates a reasonable expectation of parameters of interest, such as the evolutionary rate and age of the root node, (ii) conducting prior sensitivity analyses to assess the robustness of the posterior to the choice of prior, and (iii) selecting a molecular clock model that reasonably describes the evolutionary process.

BTI Tolerant Clock Tree Synthesis using LP-based Supply Voltage Alignment

BTI Tolerant Clock Tree Synthesis using LP-based Supply Voltage Alignment

Clinical Course and Molecular Characterization of Human Bocavirus Associated with Acute Lower Respiratory Tract Infections in a Tertiary Care Hospital in Northern India.

Respiratory samples from 139 hospitalized children were screened for the human bocavirus (HBoV) genome. Positive samples were sequenced for the partial VP1/VP2 gene followed by molecular and phylogenetic analyses. HBoV positivity was noted in 7.2% (10/139) of patients. All HBoV-positive children presented with fever, cough, and respiratory distress (90%, 9/10). Three children developed multisystemic viral illness, with one fatality. Eight children required intensive care management and five required mechanical ventilation. The nucleotide percent identity of the partial VP1/VP2 gene in the HBoV study strains ranged from 97.52% to 99.67%. Non-synonymous mutations in the VP1 protein were T591S (n = 8) and Y517S (n = 1) in the HBoV St1 strain and N475S (n = 8) and S591T (n = 2) in the HBoV St2 strain. One strain showed A556P, H556P, I561S, and M562R non-synonymous mutations. All the study strains belonged to the HBoV1 type. Seven HBoV strains belonged to the same lineage, and three belonged to another lineage. For evolutionary dynamics, GTR+I substitution model with uncorrelated relaxed lognormal clock and Bayesian Skyline tree prior showed 9.0 × 10-4 (95% highest probability density interval: 3.1 × 10-6, 2.1 × 10-3) nucleotide substitutions per site per year. Clinical suspicion and virological screening are necessary to identify HBoV infections in children.

Molecular Phylogenetics and Phylogeography of Malaysian Mousedeer (Tragulus kanchil) Based on Mitochondrial DNA Sequences of the D-Loop Region

Two sympatric mousedeer species, Tragulus kanchil and Tragulus napu, inhabit the Malaysian tropical rainforests. Previous studies have established their phylogenetic relationships based on morphological variations; however, comprehensive genetic data have yet to be extensively used to relate the relationships especially from different populations. The main objectives of this study were to determine the phylogenetic relationships, population genetics, and phylogeography of mousedeer species based on DNA sequences of the mitochondrial D-loop region. DNA from 32 mousedeer samples, representing various populations in Malaysia, was sequenced and analyzed using Neighbor-Joining, Maximum Parsimony, and Bayesian Inference approaches. The phylogenetic analyses showed two main clades representing the populations of T. kanchil and T. napu. The results also showed that the T. kanchil populations in Borneo was separated from Peninsular Malaysia taxa in MP and BI phylogenetic tree. However, Borneo population was nested in east population of Peninsular Malaysia in NJ tree. In addition, the T. kanchil population in Peninsular Malaysia further separated into east and west coast populations of Titiwangsa Range. It was supported with finding in population genetic relation that showed relatively low levels among population. This is expected because some of the populations are isolated geographically. The divergence of these populations is likely due to the Titiwangsa Range which acts as a barrier separating the east and west Peninsular Malaysia populations, and the South China Sea separates the populations of Peninsular Malaysia and Borneo. Molecular clock tree reconstruction showed that the separation of T. kanchil and T. napu occurred around 17.11 million years ago (MYAs). Furthermore, the T. kanchil populations from the east and west Peninsular Malaysia showed a branching pattern from those of Borneo of about 11.04 and 9.14 MYAs, respectively. The results of this study increase our understanding of Malaysian mousedeer phylogeny and phylogeography.

Methodology and backend flow optimization for 3D

The article deals with the complexity of the workflow used when integrated circuits are implemented using 2D electronic design automation (EDA) tools and adapting the workflow for 3D integrated circuits. If some issues are not identified promptly in the workflow, the working time to produce an integrated circuit is increased. By analyzing and refining workflow, identifying bottlenecks and early problems in a design, the optimization process will ensure an error-minimized trajectory from synthesis to final design prepared for manufacturing. Considering all the details at every stage of the working flow will help the backend designer to solve problems faster and save time. It was created detailed scripts for automatization of the process at every stage including floorplan, power plan, placement, clock tree synthesis, routing and all physical and logical analysis. The workflow was optimized using loops at all levels, extracting important information at every level and improving the process of working. Moreover, optimization techniques contribute significantly to precision and quality in design implementation. This working flow can be used to implement 3D integrated circuits with automated 2D tools from Synopsis.

An Integrated Approach towards VLSI Implementation of SFQ Logic using Standard Cell Library and Commercial Tool Suite

Abstract The semiconductor industry seeks energy-efficient alternatives as Moore’s law nears its limits. The Single Flux Quantum (SFQ) integrated circuits (ICs) using thousands of niobium Josephson junctions (JJs) and operating at 4 K show great promise for digital computing circuits at high speed (>20 GHz) and low power (a few nW per junction). The leading logic families are Rapid Single Flux Quantum (RSFQ), and its energy-efficient variant (ERSFQ). IARPA’s SuperTools program aims to develop integrated design tools for superconductor electronics, targeting SFQ and Adiabatic Quantum-Flux-Parametron (AQFP) logic families. This paper presents a passive transmission line (PTL) based standard cell library for SFQ logic, designed with Synopsys Electronic Design Automation (EDA) software tools for MIT-LL 100μA/μm2 SFQ5ee fab node. The dual RSFQ/ERSFQ standard cell library facilitates seamless integration of SFQ RTL-to-GDS design flow with Synopsys Fusion Compiler, an automated design tool. The SFQ RTL-to-GDS flow entails logic synthesis, checking, placement, clock synthesis, and routing. Row-based placement for library cells and H-tree clock tree structures are employed. Fusion Compiler’s effectiveness is validated with Hypres designs such as finite impulse response (FIR) filters, scalable multiply-accumulate (MAC) units, and memory arrays, comparing single and dual clocking schemes. The synergy between Hypres and Synopsys achieves a milestone by demonstrating the design of a digital superconducting circuit with over 10 million JJs, facilitated by a fully automated design tool for the first time. Challenges in very large-scale SFQ scaling are also discussed.

Synchronous Driving Method for Stitching Pixel Arrays Based on an Adaptive Correction Technique.

With the application of stitching technology in large-pixel-array CMOS image sensors, the problem of non-synchronized output signals from pixel array bilateral driver circuits has become progressively more serious and has led to the DC perforation of bilateral driver circuits, while conventional clock tree synchronization design methodology does not apply to stitching technology. Therefore, this paper analyses reasons for the inconsistency in the output signals of bilateral driving circuits and proposes a synchronous driving method applicable to stitching pixel arrays based on the idea of on-chip output signal delay detection and calibration. This method detects and corrects the non-synchrony of the row driver output signals on both sides according to changes in the operating environment of the chip. This method is characterized by a simple structure and high reliability. Finally, based on the 55 nm stitching process, simulations are carried out in a CMOS image sensor with a chip area of 77 mm × 84 mm to verify that this method is feasible. This large image sensor with a 150 M pixel array has a frame rate of over 10 FPS.

Advancements In Low-Power Technologies: Clock-Gated Circuits and Beyond

With the continuous advancement of the integrated circuit industry, there has been a steady rise in the level of integration and circuit scale. This inevitably leads to an escalation in power consumption by electronic devices, underscoring the growing significance of low-power technology. This comprehensive review initiates by elucidating the fundamental concept of low power, followed by an exploration of optimization measures utilizing clock-gated circuits as a prime example. Subsequently, it outlines the current challenges and prospects associated with low-power technologies. The core focus of this review revolves around the utilization of clock tree structures and triggers, which constitute the primary contributors to dynamic power consumption. These methodologies are presently the most prevalent and efficacious means to curtail power consumption through clock gating. The methodologies expounded in this review adeptly fulfill the objective of power reduction, ensuring that both present and future integrated circuits remain highly efficient. Thus, underscoring the critical role of low-power design in the realm of integrated circuit design.

A 0.55-mm2 8-bit 32-GS/s TI-SAR ADC with optimized hierarchical sampling architecture

This paper analyzes the bandwidth of the time-interleaved analog-to-digital converter (TI-ADC) with hierarchical sampling and presents an 8-bit 32-GS/s TI-ADC in 28-nm CMOS. The front-end sampler is implemented by a two-stage hierarchical sampling architecture to extend the analog input bandwidth. The 32-way sub-ADCs are realized with 2b/cycle successive approximation register (SAR) architecture and non-binary search strategy, which meet the requirements of high speed, medium resolution, and strong robustness. Multi-phase low-jitter clock tree is designed based on the delay-locked loop (DLL). Calibration methods for timing skew, offset and gain mismatches are introduced to improve accuracy. The proposed TI-SAR ADC achieves an analog input bandwidth of 23.7 GHz. It occupies an active area of 0.55 mm2 and consumes 356 mW at 1.8/1 V supply.

CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing

CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing

DEVELOPMENT OF PARAMETERIZED MODEL OF LOGIC ELEMENTS AT CLOCK TREE SYNTHESIS

Clock synthesis, routing optimization, placement and logic optimization are the three primary phases of physical design implementation. Since clock network synthesis uses at least 30% of the entire power budget, it is one of the crucial steps. Power consumption for high-performance blocks can reach 50% of the entire power. Not only would a high-quality clock tree will fix timing violations, but it will also minimize power usage and routing resource use. A new neural network based parameterized model is proposed in this paper, which can be used to obtain not only the list of logic elements, but it also can predict the circuits timing behaviour. Different ICs using SAED 14 and 32 nm technologies are designed using the proposed method.

Impact of PVT Variations on Optimizing Silicon Power

The scaling of CMOS technology faces challenges as the demand rises, but FinFETs emerging as a vital alternative for 22nm technology node and lower. Otherwise, FinFETs tend to have multiple PVT variations, making static timing analysis (STA) more flexible and suitable to analyze the timing delay of the logic generation. Device simulation and statistical temporal analysis are used to derive PVT variation models for FinFET-based standard cell designs. Mixing different FinFET design styles shows promise in optimizing delays and leakage, as FinFETs offer better control of short-channel effects and processing scalability. Furthermore, lowering clock skew is also a prime design aspect to consider. However, as technology scales to smaller devices, process, voltage, and temperature (PVT) variations make minimizing clock distortion very difficult. To mitigate the effects of PVT variations, many previous works proposed a Post Silicon Tuning (PST) architecture to dynamically balance the skew of the clock tree. In this paper, we will disclose the details of clock tree synthesis optimizations and FinFET logic developments minimizing PVT variations.

Design of a Vending Machine Using Verilog HDL and Implementation in Genus & Encounter

This paper proposes the design, implementation, and verification of a vending machine using the Finite State Machine (FSM) methodology in Verilog HDL. The FSM is used to manage the multiple states of the vending machine, including “idle,” “accepting coins,” “dispensing item,” and “returning change.” The implementation of the vending machine is done in Verilog HDL, and the FSM is implemented as a state diagram. The design is then synthesized using the Genus synthesis tool and implemented using the Encounter implementation tool. The Genus tool uses advanced optimization techniques, such as timing-driven placement and clock tree synthesis, to improve the design’s performance and area. The Encounter tool performs physical design, including placement and routing, to meet the design’s timing, power, and area constraints. To validate the design’s correctness and functionality, a test bench is created to simulate the behavior of the vending machine. The simulation results are then used to verify that the design meets the required specifications and that the FSM behaves as expected. The proposed design is then can be implemented on a Field Programmable Gate Array (FPGA) to demonstrate its effectiveness in a real-world scenario. The results of the implementation are presented and analyzed to validate the design’s performance, power consumption, and area. Overall, the vending machine using FSM in Verilog HDL, implemented in Genus and Encounter, provides a reliable and efficient solution for users to purchase items from the machine. The proposed design and implementation demonstrate the feasibility and effectiveness of this approach, and the results show that the design meets the required specifications and performs well in a real-world scenario.

Machine learning in physical design

Machine learning is a highly effective instrument in constructing models that can expeditiously produce accurate prognostications. As the complexity of integrated circuit design continues to increase and process nodes continue to evolve, and physical design faces more challenges from modeling and optimization. To address these challenges, machine learning has been introduced into physical design. Thus, in this paper, we discuss the application of machine learning in physical design, covering topics such as Clock Tree Synthesis (CTS), Placement and Routing, IR-Drop and Static Timing Analysis (STA). The essay explores how machine learning can be used to overcome challenges in these areas, such as reducing peak current and clock skew in CTS, optimizing placement parameters and decision-making, predicting routability and reducing IR-drop effects. This paper also discusses various machine learning techniques (ML), such as reinforcement learning, convolutional neural networks and transfer learning. To conclude, we provide insights into how machine learning can be applied to improve various aspects of physical design.

A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route

Due to the unavailability of routing information in design stages prior to detailed routing (DR), the tasks of timing prediction and optimization pose major challenges. Inaccurate timing prediction wastes design effort, hurts circuit performance, and may lead to design failure. This work focuses on timing prediction after clock tree synthesis and placement legalization, which is the earliest opportunity to time and optimize a “complete” netlist. The article first documents that having “oracle knowledge” of the final post-DR parasitics enables post-global routing (GR) optimization to produce improved final timing outcomes. To bridge the gap between GR-based parasitic and timing estimation and post-DR results during post-GR optimization , machine learning (ML)-based models are proposed, including the use of features for macro blockages for accurate predictions for designs with macros. Based on a set of experimental evaluations, it is demonstrated that these models show higher accuracy than GR-based timing estimation. When used during post-GR optimization, the ML-based models show demonstrable improvements in post-DR circuit performance. The methodology is applied to two different tool flows—OpenROAD and a commercial tool flow—and results on an open-source 45nm bulk and a commercial 12nm FinFET enablement show improvements in post-DR timing slack metrics without increasing congestion. The models are demonstrated to be generalizable to designs generated under different clock period constraints and are robust to training data with small levels of noise.

Design Automation Framework for Placement and Clock Tree Synthesis of Superconducting Rapid Single-Flux-Quantum Logic

Design Automation Framework for Placement and Clock Tree Synthesis of Superconducting Rapid Single-Flux-Quantum Logic

Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs

Clock tree synthesis (CTS) is an important process in determining overall chip timing and power consumption. The CTS is also a time-consuming process for checking the clock tree. If the chip design and specification do not match, the CTS result will be wrong. Many users use licensed electronic design automation (EDA) tools like Synopsys, and Cadence to carry out accurate chip verification. However, when using a licensed EDA tool, it is difficult to change the function and confirm the overall process in detail. If the design is wrong, the expected cost is doubled, as it will be necessary to modify the design and check all processes for verification. Currently, it cannot check the synthesizability of the clock tree on the placement and route process using only RTL. The main purpose of this study is to predict the CTS result of pre-estimation roughly using an RTL source placing temporary logics using random buffer insertion before the route process: then the incorrectly designed part can be freely modified because the CTS result can be known in advance. Experimental results showed that this research achieves an increase in inserted buffer area by about 10%, the standard deviation of clock skew achieves zero clock skew after shallow CTS, and clock frequency increases by about 10%. This paper contributes to optimizing clock tree implementation by conducting the pre-route process before using the CTS tool. Also, our approach not only minimizes resource usage but also optimizes CTS for the RTL structure. It holds considerable value in enhancing the efficiency and performance of integrated circuits.

Molecular Identification and Evolutionary Divergence of the Sri Lankan Sambar Deer, Rusa unicolor (Kerr 1792).

The Sambar is one of the largest deer species distributed mainly in Asia, and it has been listed as a vulnerable species. Taxonomy based on morphological characterization has been the gold standard method used to identify the Sambar deer species. Yet, morphological identification is challenging and requires expertise. To conduct species identification and taxonomic decisions, we performed the molecular identification of R. unicolor found in Sri Lanka using DNA barcodes, COI, and Cyt b to compare the Sri Lankan R. unicolor with the Indian R. unicolor and other R. unicolor subspecies. We obtained mitochondrial DNA sequences from COI and Cyt b from blood samples collected from the wet zone in Sri Lanka. A phylogenetic tree was constructed based on the Bayesian analyses using MrBayes 3.2.7. Molecular dating was implemented in Bayesian Evolutionary Analysis Sampling Trees (BEAST v1.8.2) on the concatenated sequence using a log-normal relaxed clock and Yule species tree prior, with four categories. The results showed that the Sri Lankan R. unicolor is genetically different from the Indian R. unicolor and other R. unicolor subspecies. The divergence occurred approximately 1.1 MYA (million years ago) in the Pleistocene era. The results are essential for designing new conservation platforms for these Sambar deer species.

A PPA Study of Reinforced Placement Parameter Autotuning: Pseudo-3D vs. True-3D Placers

D Place and Route (P&R) flows either involve true-3D placement algorithms or use commercial 2D tools to transform a 2D design into a 3D design. Irrespective of the nature of the placers, several placement parameters in these tools affect the quality of the final 3D designs. Different parameter settings work well with different circuits, and it is impossible to manually tune them for a particular circuit. Automated approaches involving reinforcement learning have been shown to adapt and learn the parameter settings and create trained models. However, their effectiveness depends on the input dataset quality. Using a set of 10 netlists and 10–21 handpicked placement parameters in P&R flows involving pseudo-3D or true-3D placement, the dataset quality is analyzed. The datasets are the design metrics obtained through different P&R stages, such as placement optimization, clock tree synthesis, or 3D partitioning and global routing. The training runtime and the quality of the final design metrics are compared. On a pseudo-3D flow, the training takes around 126–290 hours, whereas, on a true-3D placer-based flow, it takes around 305–410 hours. It is observed that the datasets obtained from different stages lead to drastically different final design results. With the RL-based training processes, the quality of results in 3D designs improves by up to 23.7% compared to their corresponding untrained P&R flows.

Clock tree generation by abutment in synchoros VLSI design

Synchoros VLSI design style has been proposed as an alternative to standard cell-based design. Standard cells are replaced by synchoros, large grain, VLSI design objects called SiLago (Silicon Lego) blocks. This new design style eliminates the need to synthesise ad hoc wires of any type: functional and infrastructural. SiLago blocks are organised into region instances. In a region instance, communication amongst SiLago blocks is synchronous and happens over a regional network on chip (NoC), whose fragments are also absorbed into SiLago blocks. Consequently, the regional NoCs get created by the abutment of SiLago blocks. The clock tree used in a region is called a regional clock tree (RCT). The synchoros VLSI design style requires that the RCT, like the regional NoCs, is also created by abutting its fragments. The RCT fragments are absorbed within the SiLago blocks. The RCT created by the abutment is not an ad-hoc clock tree but a structured and predictable design with known cost metrics. The design of such an RCT is the focus of this paper. The scheme is scalable, and we demonstrate that the proposed RCT can be generated for valid VLSI designs of ∼1.5 million gates. The RCT created by abutment is correct by construction, and its properties are predictable. Additionally, we present an in-depth description of the method used to find the optimal configuration for the proposed design. We have validated the generated RCTs with static timing analysis to validate the correct-by-construction claim. Finally, we show that the cost metrics of the SiLago RCT is comparable to the one generated by commercial EDA tools.